Memory Built-In Self-Test Interruption via Mode Segmentation
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Solution Overview
Problem
Memory devices, particularly in safety-critical applications like automobiles, face challenges with memory built-in self-test (MBIST) procedures that cannot be interrupted, leading to prolonged downtime and potential safety risks due to the inability to pause testing and repair processes during soldering or integration, which may introduce errors.
Innovation Solution
The MBIST procedure is separated into a test mode and a repair mode, allowing the memory device to interrupt the test mode but not the repair mode, reducing the overall duration of MBIST and enhancing performance, reliability, and safety by shortening the time during which the device is unavailable for normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the MBIST procedure is performed continuously without interruption to ensure complete testing and repair, then the reliability and safety are improved, but the downtime and loss of time increase significantly
Solution Approach 1:
The MBIST procedure is segmented into distinct test mode and repair mode phases. The test mode performs comprehensive memory testing while the repair mode handles repairs. This segmentation allows the system to interrupt the test mode when necessary (reducing downtime) while ensuring the repair mode completes fully (maintaining reliability).
Solution Approach 2:
The MBIST procedure is made dynamic by allowing interruption during the test mode based on system needs, while the repair mode runs to completion. This dynamic approach enables the system to adapt the MBIST execution to real-time requirements, balancing reliability assurance with minimal downtime.
2Loss of time
If the MBIST procedure is interrupted during testing to reduce downtime, then the loss of time is reduced, but the measurement precision and completeness of testing deteriorate
Solution Approach 1:
By separating the MBIST into test mode and repair mode, the invention allows interruption during test mode without compromising overall testing completeness. The test mode can be restarted or resumed, while the repair mode ensures all identified issues are addressed, maintaining measurement precision.
Solution Approach 2:
The test mode performs preliminary identification of memory issues before the repair mode executes comprehensive repairs. This preliminary action allows the system to interrupt and resume testing while ensuring that all issues are eventually detected and addressed, maintaining testing completeness.
3Reliability
If the MBIST procedure is performed on the entire memory array to ensure complete coverage, then the reliability is improved, but the duration of action and productivity decrease
Solution Approach 1:
The memory array testing is segmented into test mode and repair mode operations. The test mode can be configured to test specific regions or the entire array, while the repair mode handles repairs. This segmentation allows flexible testing coverage that maintains reliability while improving productivity by enabling selective testing and faster repair completion.
Solution Approach 2:
The system can perform partial testing during test mode if full array testing is not immediately necessary, allowing the device to remain partially operational. The repair mode then ensures comprehensive repair of any identified issues. This partial action approach maintains adequate reliability while improving device availability and productivity.
Data Source
AI summary
Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.