Memory Module BIST Priority Control for Reliability
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Solution Overview
Problem
Existing memory module testing methods, such as ECC technology, compromise system efficiency to ensure reliability, and traditional BIST methods may damage products during handling and usage, leading to reliability concerns without adequate active quality assurance.
Innovation Solution
A memory module with a built-in self-test (BIST) method that prioritizes system commands over BIST commands during data access, allowing for self-testing without disrupting normal operations, using a memory control unit and BIST control unit to manage data access and testing within memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC technology is used to guarantee memory reliability, then memory reliability is improved, but system efficiency deteriorates with about 5% efficiency loss
Solution Approach 1:
The patent implements preliminary action by performing BIST testing during idle periods or power-on states before normal system operations begin. The memory controller executes self-diagnostic tests on memory banks during initialization or when no system commands are pending, thereby detecting potential failures before they affect system efficiency. This approach ensures reliability through proactive testing while avoiding the continuous overhead that would reduce productivity.
2Reliability
If traditional BIST method is used to test memory, then memory reliability is improved, but system effectiveness deteriorates due to disruption of normal operations
Solution Approach 1:
The patent applies dynamics by making the BIST testing process adaptive and flexible rather than static and disruptive. The memory controller dynamically schedules BIST commands based on system workload conditions, choosing to execute tests during idle periods or low-utilization states. This dynamic approach allows the system to maintain high effectiveness during normal operations while still performing comprehensive memory reliability testing when appropriate, thus resolving the contradiction between reliability improvement and effectiveness maintenance.
3Reliability
If continuous memory testing is performed to ensure quality, then memory reliability is improved, but system performance deteriorates due to constant testing overhead
Solution Approach 1:
The patent implements periodic action by scheduling memory BIST testing at specific intervals rather than continuously. The memory controller performs self-diagnostic tests during power-on initialization, after detecting idle periods, or at predetermined time intervals when system performance requirements are lower. This periodic testing approach ensures memory quality is maintained through regular checks while avoiding the continuous performance degradation that would result from constant testing, thereby resolving the contradiction between reliability improvement and time loss.
Data Source
AI summary
A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.