Semiconductor Memory BIST Circuit Self-Testing
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Solution Overview
Problem
Conventional methods for testing semiconductor memory devices require external test devices, leading to either prolonged test times when the external device operates at a lower frequency or high costs when it operates at the same frequency as the semiconductor device.
Innovation Solution
Incorporating built-in self-test (BIST) circuits within the semiconductor memory device to generate and compare test pattern data, reducing the need for external test devices by performing memory tests internally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external memory test device is used to test semiconductor memory device, then testing can be performed, but test time becomes relatively long when external device operates at lower frequency
Solution Approach 1:
The semiconductor memory device performs self-testing using built-in BIST circuits that generate test patterns and compare them with data read from the memory array. This eliminates the need for external test devices to conduct the actual testing, allowing the device to test itself at its own operating frequency without being constrained by the external device's lower frequency, thereby significantly reducing test time.
Solution Approach 2:
The testing function is segmented into two parts: the semiconductor memory device performs the actual memory testing operations using its internal BIST circuits, while the external test device only provides test control signals and receives test results. This segmentation allows the memory device to operate at its full speed during testing without being limited by the external device's lower operating frequency.
2Productivity
If external memory test device operates at identical frequency to semiconductor memory device, then test speed is maximized, but cost increases significantly
Solution Approach 1:
By equipping the semiconductor memory device with built-in BIST circuits, the device becomes self-sufficient for testing purposes. The internal pattern generator creates test patterns, the comparator verifies memory operations, and the output buffer transmits results - all without requiring an expensive external test device operating at matching high frequency. This dramatically reduces testing costs while maintaining high test throughput at the memory device's operating frequency.
3Loss of time
If built-in self-test circuit is incorporated in semiconductor memory device, then test time is reduced, but device complexity increases
Solution Approach 1:
The BIST circuit is designed to perform all necessary testing functions internally using standard logic components including pattern generators, comparators, and output buffers. These circuits are integrated directly into the memory device architecture, enabling self-testing capability that reduces dependence on external equipment while adding only moderate complexity compared to the overall device.
4Device complexity
If conventional external testing method is used, then device complexity remains low, but testing cost and time increase
Solution Approach 1:
The testing system is segmented such that the semiconductor memory device contains embedded BIST circuits for actual testing operations, while the external test device is simplified to only provide control signals and capture results. This segmentation transfers the complex testing functionality from the external device to the memory device itself, reducing external device complexity while significantly improving testing efficiency through high-speed internal operation.
Data Source
AI summary
A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test pattern data.