Semiconductor Memory BIST Sync Read Control Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory device screening tests are time-consuming and costly due to the inability to implement BIST for the read operation system's control and sense amplifier circuits, requiring additional tests even if defects occur in these circuits.
Innovation Solution
Incorporating an auto-operation control circuit, sync read control circuit, read control circuit, read sense amplifier circuit, and determination circuit to perform a sync read test, allowing for self-testing and comparison of read data with expectation values, thereby enabling comprehensive screening within the BIST framework.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional screening test methods are used, then the read control circuit and read sense amplifier circuit cannot be screened during BIST test, but implementing additional tests increases test time and test cost
Solution Approach 1:
The patent merges the read control circuit and read sense amplifier circuit into the BIST test framework by introducing a sync read control circuit that coordinates these circuits with the auto-operation control circuit. This integration allows the read operation system to be screened during the BIST test without requiring separate additional tests, thereby reducing test time while maintaining comprehensive screening capability.
Solution Approach 2:
The sync read control circuit is designed to perform multiple functions: it controls the read operation system during normal operation and simultaneously enables BIST testing of the read control circuit and read sense amplifier circuit. This multi-functionality allows a single circuit to serve both operational and testing purposes, eliminating the need for separate test circuits and reducing overall test time.
2Reliability
If conventional screening test methods are used, then the read control circuit and read sense amplifier circuit cannot be screened during BIST test, but implementing additional tests increases test cost
Solution Approach 1:
The patent combines the screening of read control circuit and read sense amplifier circuit with the existing BIST test process. By integrating these circuits into the auto-operation control framework through the sync read control circuit, the patent eliminates the need for separate test equipment and procedures, thereby reducing test cost while maintaining comprehensive screening capability.
Solution Approach 2:
The auto-operation control circuit and sync read control circuit are designed to serve dual purposes: normal memory operation and BIST testing. This universality allows the same hardware infrastructure to be used for both production and testing, reducing the need for additional specialized test equipment and lowering overall test cost.
3Reliability
If only auto-operation system circuits are used for BIST test, then the read operation system circuits cannot be tested, but adding read operation system testing requires additional test steps
Solution Approach 1:
The patent merges the read operation system circuits into the BIST test framework by introducing a sync read control circuit that coordinates the read control circuit and read sense amplifier circuit with the auto-operation control circuit. This integration allows comprehensive testing of both auto-operation and read operation system circuits within a unified test architecture, increasing test coverage without requiring entirely separate test systems.
Solution Approach 2:
The sync read control circuit acts as an intermediary between the auto-operation control circuit and the read operation system circuits. It translates and coordinates control signals to enable the read control circuit and read sense amplifier circuit to function within the BIST framework, thereby extending test coverage to the read operation system without directly increasing the complexity of the core BIST architecture.
Data Source
AI summary
A semiconductor memory device includes a semiconductor memory, an auto-operation control circuit which outputs a clock signal, a sync read control circuit which outputs a sync read address in sync with the clock signal, a read control circuit which selects a read address of the semiconductor memory in accordance with an address of the sync read address, a read sense amplifier circuit which outputs a data read signal that is produced by sensing data that is read out of the semiconductor memory in accordance with the read address, and a determination circuit which compares the data read signal with an expectation value.