Non-volatile Memory Bit Cell Biasing for Power and Speed
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Solution Overview
Problem
Conventional memory devices face high power consumption and slow data read operations due to the application of positive voltages to multiple bit cells, which can also alter stored data unintentionally.
Innovation Solution
A memory system that employs a low power read mode by biasing bit cells at a negative voltage to reduce power consumption and improve speed, and a margin read mode by applying positive voltages to ensure accurate data retrieval after programming or erasing, using a configuration that includes a non-volatile memory array, control line, word line, and bit line controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If positive voltages are applied to multiple bit cells for data read operations, then data can be sensed from selected bit cells, but power consumption increases and read operation time extends
Solution Approach 1:
The patent inverts the conventional approach by applying negative voltages instead of positive voltages to bit cells during read operations. Specifically, negative voltages are applied to unselected bit cells to suppress leakage currents, while selected bit cells are read with minimal voltage disturbance. This inversion resolves the contradiction by reducing power consumption while maintaining data sensing capability.
Solution Approach 2:
The patent applies different voltage conditions to different groups of bit cells: negative voltages are applied to unselected bit cells to minimize leakage and power consumption, while selected bit cells receive appropriate voltages for data sensing. This localized differentiation allows the system to reduce overall power consumption while maintaining the necessary data read capability for selected cells.
2Measurement precision
If positive voltages are applied to multiple bit cells for data read operations, then data can be sensed from selected bit cells, but the time to perform the data read operation increases
Solution Approach 1:
By inverting the voltage application strategy to use negative voltages on unselected bit cells, the patent reduces leakage currents and stabilizes the reading environment. This allows for faster read operations as the system doesn't need to manage the time-consuming effects of leakage currents and voltage conflicts that occur with conventional positive voltage application to multiple bit cells.
3Measurement precision
If positive voltages are applied to multiple bit cells for data read operations, then data can be sensed from selected bit cells, but changes of charges stored in the multiple bit cells occur altering the stored data unintentionally
Solution Approach 1:
The patent applies negative voltages to unselected bit cells during read operations, which suppresses leakage currents and prevents unwanted charge changes. This inversion of the conventional positive voltage approach ensures that only the selected bit cell experiences voltage conditions sufficient for data sensing, while other bit cells remain electrically stable, thus preserving data integrity across the memory array.
Solution Approach 2:
The patent implements local voltage differentiation where selected bit cells receive the necessary voltage conditions for data sensing, while unselected bit cells are maintained at negative voltages to prevent charge leakage and data alteration. This localized voltage control ensures that data integrity is maintained in unselected cells while enabling successful read operations in the selected cell.
Data Source
AI summary
A memory system with improved power consumption and operation speed. A memory system performs a data read operation in a low power read mode to improve operation speed and reduce power consumption by biasing bit cells in the memory system at a negative voltage. The use of the negative voltage minimizes changing of voltages of the bit cells. Additionally, the memory system performs data read operation in a margin read mode to improve accuracy of the reading by biasing the bit cells at a positive voltage.