Memory Bit Cell Level Shifter for Low Voltage Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Electronic devices face stability issues in memory devices when operating at low voltages, as they tend to decrease with increased speed, necessitating a memory bit cell that can latch data at a higher voltage and an effective method to interface such a cell within the device.
Innovation Solution
A memory array design incorporating a level shifter in each memory bit cell with a write port featuring p-type and n-type field effect transistors, where the control and current electrodes are connected to form common nodes, allowing operation at different voltage levels (VddL and VddH) to prevent transistor damage and ensure stable data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory devices operate at lower voltages to conserve power, then power consumption is reduced, but stability decreases
Solution Approach 1:
The memory device is segmented into different operational modes with distinct voltage levels. The memory cell can operate in a first mode at a first voltage level and switch to a second mode at a second voltage level, allowing different parts of the system to operate at different voltages simultaneously. This segmentation resolves the contradiction by enabling low-power operation when stability requirements are low, while providing high-stability operation when needed.
Solution Approach 2:
The memory device employs dynamic voltage switching capability. The control circuit dynamically adjusts the operating voltage of the memory cell based on operational requirements, transitioning between first and second voltage levels. This dynamic adaptation allows the system to optimize the balance between power consumption and stability according to real-time needs.
2Speed
If memory devices increase speed, then processing performance improves, but stability decreases at lower voltages
Solution Approach 1:
The system segments operational requirements into different voltage modes. High-speed operations can utilize the second voltage level for improved performance, while maintaining the first voltage level for stable, power-efficient operation. This segmentation allows the memory device to achieve high speeds when necessary without compromising stability during normal operation.
Solution Approach 2:
The invention changes the voltage parameter dynamically based on operational mode. By switching between first and second voltage levels, the system can optimize both speed and stability according to the specific operational requirements, resolving the trade-off between processing speed and stability.
3Reliability
If a memory bit cell latches data at a higher voltage, then stability improves, but device complexity increases
Solution Approach 1:
A control circuit acts as an intermediary between the memory cell and the external interface. This control circuit manages the voltage level transitions and coordinates the switching between first and second operational modes, simplifying the overall interface complexity while maintaining the ability to latch data at higher voltages for improved stability.
Solution Approach 2:
The memory cell is designed with multi-functionality to operate at multiple voltage levels. The same memory cell structure can latch data at a first voltage level for normal operation and switch to a second, higher voltage level for enhanced stability, eliminating the need for separate memory cells for different voltage requirements and reducing overall device complexity.
Data Source
AI summary
The present application discloses a memory array where each memory bit cell of the array includes a level shifter. In addition, each memory bit cell includes a write port that includes pass gate that can include a p-type field effect transistor and an n-type field effect transistor. The control electrodes of the p-type field effect transistor and the n-type field effect transistor are connected together as part of a common node. In addition, a current electrode of the p-type field effect transistor and a current electrode of the n-type field effect transistor are connected together to form a common node.