Memory Sub-System Bit-Per-Cell Switching for Thermal Reliability
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Solution Overview
Problem
The thermal limitations of memory devices, such as NAND flash memory, restrict the performance of computing systems due to their lower maximum operating temperature compared to other components like ASICs and DRAM, leading to performance throttling and reliability issues under high computational demand.
Innovation Solution
Reconfiguring memory devices to store a lesser number of bits per memory cell based on temperature, thereby broadening the threshold voltage distribution valleys and reducing the likelihood of data interpretation errors, allowing higher operating temperatures without compromising reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory devices operate at higher temperatures to match ASIC and DRAM thermal limits, then system performance and burst speeds improve, but data reliability and threshold voltage stability deteriorate
Solution Approach 1:
The patent implements dynamic reconfiguration of memory devices that allows the system to adaptively change operational parameters based on real-time temperature conditions. The memory device transitions between different modes (e.g., SLC/MLC/TLC configurations) depending on thermal state, enabling high-performance operation when cool and reliable operation when hot, thus resolving the contradiction between sustained high performance and data reliability across varying temperature conditions.
Solution Approach 2:
The patent changes physical parameters of the memory device, specifically the number of bits stored per cell and threshold voltage distribution characteristics. By adjusting these parameters dynamically based on temperature, the system maintains optimal reliability across different thermal conditions while preserving the ability to achieve high burst speeds when temperature permits.
2Quantity of substance
If memory devices store more bits per memory cell to increase storage density, then storage capacity improves, but threshold voltage distribution valleys narrow and reliability at high temperatures worsens
Solution Approach 1:
The memory device dynamically reconfigures its storage density based on operating conditions. When temperature is low, the device operates in high-density modes (TLC, QLC) with more bits per cell. When temperature rises, it transitions to lower-density modes (SLC, MLC) with wider threshold voltage valleys, thus maintaining reliability while maximizing storage utilization under optimal conditions.
Solution Approach 2:
The patent changes the storage configuration parameter (bits per cell) based on temperature conditions. This parameter change directly affects the threshold voltage distribution characteristics, creating wider valleys at high temperatures for reliability while enabling higher density when temperatures are favorable.
3Productivity
If memory devices operate continuously at high burst speeds to maximize productivity, then system performance improves, but temperature increases and thermal throttling occurs
Solution Approach 1:
The patent implements periodic temperature monitoring and adaptive performance adjustment. Instead of continuous high-speed operation, the system periodically checks temperature conditions and adjusts burst speeds accordingly, creating a rhythm of high-performance intervals followed by thermal management intervals, thus sustaining overall productivity while preventing dangerous temperature accumulation.
Solution Approach 2:
The system employs feedback control where temperature measurements feed back to adjust operational parameters. When temperature rises during high-speed operation, the system receives feedback and dynamically reduces burst speeds or activates cooling measures, creating a self-regulating mechanism that maintains productivity within safe thermal boundaries.
Data Source
AI summary
A processing device in a memory sub-system receives a request to write data to the memory device, wherein the memory device is configured to store a first number of bits per memory cell. The processing device obtains a temperature measurement of the memory device. Responsive to determining that the temperature measurement of the memory device satisfies a first operating temperature threshold criterion, the processing device reconfigures the memory device to store a second number of bits per memory cell, wherein the first operating temperature threshold criterion is associated with the first number of bits per memory cell, and wherein the second number of bits per memory cell is less than the first number of bits per memory cell. The processing device performs a write operation to store the data in the memory device using the second number of bits per memory cell.