Memory Bit Reordering Circuit for Per-Bit Defect Repair
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Solution Overview
Problem
Conventional memory repair methods require additional space and complexity to replace defective memory bits, which is inefficient as memory size decreases and capacity increases, leading to increased waste and slower processing speeds.
Innovation Solution
A reordering circuit and method that selectively replaces defective memory bits with redundancy bits on a per-bit basis, using simple logic gates to determine defective bits and unused redundancy, reducing area requirements and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row or column redundancy method is used to replace defective memory bits, then defective bits can be repaired, but entire rows or columns including good memory bits are also replaced causing waste and requiring large area
Solution Approach 1:
The patent divides the memory array into multiple sub-arrays and implements independent redundancy repair for each sub-array. Instead of replacing entire rows or columns across the whole memory, the repair is segmented to affect only local regions, thereby reducing the overall redundancy space requirement while maintaining repair capability.
Solution Approach 2:
The patent applies local quality by implementing repair mechanisms that are tailored to specific defective regions rather than applying uniform row/column redundancy across the entire memory. Each sub-array can have its own redundancy configuration optimized for its specific defect pattern, reducing total redundancy overhead.
2Reliability
If conventional row or column redundancy method is used, then defective bits can be repaired, but the circuit complexity increases and processing speed decreases
Solution Approach 1:
The repair circuit is segmented into multiple independent determination circuits, each responsible for a specific sub-array. This segmentation distributes the circuit complexity across multiple simple units rather than requiring one complex centralized repair circuit, reducing overall device complexity while maintaining repair functionality.
Solution Approach 2:
The patent implements repair determination for only the necessary portions of memory (specific sub-arrays with defects) rather than continuously monitoring or repairing the entire memory array. This partial action approach reduces circuit complexity by activating repair mechanisms only when and where needed.
Data Source
AI summary
A method of reordering memory bits includes steps of: providing multiple pieces of bit repair data corresponding to memory bits and used to mark whether any one of the memory bits is defective bit; generating selection signals based on multiple pieces of bit repair data; selecting and coupling good memory bits of the memory bits to multiple input/output terminals of a memory, respectively, based on the multiple pieces of bit repair data and the selection signals or based on the selection signals.