Memory Bit Error Remapping to Spare Lanes
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Solution Overview
Problem
Current memory systems face challenges in efficiently managing multibit errors, as parity bit checking can only detect single bit errors and lacks the mechanism to correct data errors, affecting the recoverability, availability, and serviceability (RAS) of high-end systems.
Innovation Solution
A memory system that includes a plurality of memory devices configured to work together as a rank, with a memory control circuit capable of detecting bit errors and remapping them to a spare bit lane, along with error correction code (ECC) for data and location information, allowing for efficient error correction and data reconstruction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bit checking is used for error detection, then single bit errors can be detected, but multibit errors cannot be corrected and data recovery is limited
Solution Approach 1:
The patent segments the data storage structure by introducing separate spare bit lanes distinct from the data bits and parity bits. This segmentation allows independent management of error correction functions, enabling the system to handle multibit errors that traditional parity checking cannot address.
Solution Approach 2:
The patent implements preliminary action by pre-allocating spare bit lanes in the memory structure before errors occur. These spare bits are ready to receive corrected data immediately when errors are detected, eliminating the need for complex real-time correction algorithms and enabling efficient multibit error recovery.
2Device complexity
If traditional parity bit checking is used, then error detection is simple, but system RAS (Recoverability, Availability, Serviceability) capabilities are insufficient
Solution Approach 1:
The spare bit lanes serve multiple functions: they store corrected data for error recovery, maintain system availability during failures, and provide serviceability information for error management. This multi-functionality enhances RAS capabilities without requiring separate dedicated systems for each function.
Solution Approach 2:
The memory control circuit acts as an intermediary between error detection and data recovery operations. It manages the coordination between parity checking, spare bit allocation, and data reconstruction, enabling sophisticated error handling while maintaining system reliability.
3Quantity of substance
If higher density memory devices are used to increase capacity, then storage capability improves, but error management becomes more challenging
Solution Approach 1:
The patent adds a dimensional aspect to error management by introducing spare bit lanes as a separate dimension in the memory architecture. This additional dimension provides dedicated space for error correction without consuming storage capacity, allowing high-density memory systems to maintain robust error management capabilities.
Data Source
AI summary
A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.