Memory Codeword Bit Flipping With Concurrent Flip-Bit Generation
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Solution Overview
Problem
Memory systems face significant latency due to propagation delays and increased throughput issues when performing error correction on inversion bits, which delays read operations and affects the reliability of bit flipping in memory devices.
Innovation Solution
Implementing an enhanced bit flipping scheme that generates flip bits concurrently with error correction, using alternative error correction techniques such as voting schemes and robust sensing methods to increase the reliability of flip bits without incurring propagation delays, and storing multiple inversion bits to determine the state of data bits within a codeword.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed on inversion bits before read operations, then reliability of data retrieval is improved, but latency and propagation delays increase
Solution Approach 1:
The system performs error correction on inversion bits in advance during write operations or idle periods, so that when read operations occur, the correction is already complete. This preliminary action eliminates the need to wait for error correction during read operations, thereby maintaining high reliability while reducing latency.
Solution Approach 2:
The error correction process is segmented into independent stages that can be executed separately from the main read operation timeline. By dividing the correction task into pre-processing steps and parallel execution paths, the system maintains reliability without blocking the read operation, thus reducing overall latency.
2Reliability
If error correction operations are performed on inversion bits, then data accuracy is improved, but throughput decreases due to propagation delays
Solution Approach 1:
The system maintains continuous data flow by executing error correction operations in parallel with other processing tasks rather than sequentially. Multiple correction operations can occur simultaneously across different data paths, ensuring that data accuracy is maintained while throughput remains high due to uninterrupted processing.
Solution Approach 2:
Error correction is performed in advance before the main data processing pipeline, so that by the time data needs to be processed, correction is already complete. This preliminary action ensures data accuracy without creating bottlenecks that would reduce overall system throughput.
3Reliability
If traditional error correction schemes are used for inversion bits, then reliability is improved, but significant latency is introduced into the memory system
Solution Approach 1:
The system performs error correction on inversion bits in advance during write operations or idle periods, so that when read operations occur, the correction is already complete. This preliminary action eliminates the need to wait for error correction during read operations, thereby maintaining high reliability while reducing latency.
Solution Approach 2:
The error correction timing is made dynamic rather than fixed, allowing the system to perform correction at optimal moments based on current operational state. When latency would be problematic, correction is performed in advance; when resources are available, correction can be deferred or parallelized, thus maintaining reliability while adapting to minimize latency.
Data Source
AI summary
Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.