Memory Bit Flipping Scheme for Parallel ECC and Flip-Bit Generation
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Solution Overview
Problem
Current memory systems experience significant latency due to propagation delays and serial control operations when performing error correction for bit inversion, which can be exacerbated by the distribution of control information across large memory sections, leading to decreased throughput and reliability.
Innovation Solution
The implementation of an enhanced bit flipping scheme that refrains from performing error correction on inversion bits until after syndrome bits have been distributed, allowing for concurrent error correction of data bits and generation of flip bits, using alternative error correction techniques such as voting schemes or robust sensing to maintain reliability without increasing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed on inversion bits before generating flip bits, then reliability is improved, but latency increases due to propagation delays and serial control operations
Solution Approach 1:
The patent performs preliminary error correction on data bits before the inversion bit is fully processed. By pre-computing syndrome bits and performing data bit correction in advance, the system reduces the critical path delay while maintaining reliability through staged error correction.
Solution Approach 2:
The patent segments the error correction process into independent stages: syndrome bit generation, data bit error correction, and inversion bit processing. This segmentation allows parallel execution of data bit correction and inversion bit handling, reducing aggregate propagation delays while maintaining overall reliability.
2Reliability
If error correction is performed serially on all bits including inversion bits, then reliability is improved, but throughput decreases due to compounded propagation delays
Solution Approach 1:
The patent divides the error correction workflow into segmented, parallelizable stages: syndrome computation, data bit correction, and inversion bit processing. Each stage can be executed independently or in parallel, transforming a serial bottleneck into a pipelined process that maintains reliability while improving throughput.
Solution Approach 2:
The patent maintains continuous useful action by overlapping error correction operations with memory access operations. Syndrome bits are generated and processed continuously rather than waiting for complete inversion bit processing, keeping the error correction pipeline full and maximizing throughput without sacrificing reliability.
3Quantity of substance
If inversion bits are distributed across large memory sections, then memory capacity is improved, but latency increases due to propagation delays in control operations
Solution Approach 1:
The patent segments large memory sections into smaller sub-sections or banks, each with its own inversion bit handling. This segmentation reduces the propagation distance for control operations while maintaining overall memory capacity, as each segment can be independently and concurrently accessed and corrected.
Solution Approach 2:
The patent performs preliminary identification and marking of inversion bits during the read operation setup phase, before the actual data retrieval. This preliminary action allows the system to prepare correction strategies in advance, reducing the time required during the critical data access phase despite distributed inversion bits across large memory sections.
Data Source
AI summary
Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.