Memory Controller Bit Flipping for Low-Power SCM Writes
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Solution Overview
Problem
In storage class memory systems, the imbalance in the number of '0' and '1' bits in data sequences leads to inefficient writing operations, as writing '0's requires more power-consuming reset operations, which reduces memory cell endurance and increases power consumption.
Innovation Solution
A method where the memory controller flips bits in data sequences with more '0's than '1's to favor writing sequences with more '1's, reducing the need for reset operations and improving endurance by inverting bits when the difference in bit counts exceeds a threshold, and storing a flip flag for potential reverse operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is written directly to memory device without bit flipping, then writing operation is simple and fast, but power consumption increases and memory cell endurance decreases due to excessive reset operations
Solution Approach 1:
The memory controller performs preliminary bit flipping operations on incoming data before writing to the memory device. By analyzing the bit distribution and flipping bits in advance when the difference between '0' and '1' counts exceeds a threshold, the system prepares optimized data patterns that reduce the number of reset operations needed during the actual write operation, thereby lowering power consumption and improving endurance.
2Duration of action of stationary object
If bit flipping operation is performed to balance '0' and '1' bits, then reset operations are reduced and endurance is improved, but additional processing time and complexity are introduced
Solution Approach 1:
The system dynamically changes the data pattern parameters by flipping bits based on the bit distribution analysis. When the difference between the number of '0' bits and '1' bits exceeds a predetermined threshold, the system applies bit flipping to balance the distribution, thereby reducing the number of reset operations and improving memory cell endurance while managing processing overhead through threshold-based decision making.
3Reliability
If more reset operations are performed to write '0' bits, then data accuracy is maintained, but power consumption increases and memory cell durability decreases
Solution Approach 1:
Instead of directly writing data patterns that may require excessive reset operations, the system inverts the approach by flipping bits in advance to create balanced data patterns. This inversion strategy ensures that the written data maintains accuracy while significantly reducing the number of power-consuming reset operations needed during the write process, thereby lowering overall power consumption and improving memory cell durability.
Data Source
AI summary
A memory system includes a memory device including memory cells, and a memory controller coupled to the memory device. A memory cell is configured to be programmed to one of a first state and a second state. The first state corresponds to a first bit, and the second state corresponds to a second bit. The memory controller is configured to receive first data including bits, the bits of the first data including the first bit and the second bit, in response to a second number of the second bit in the first data being larger than a first number of the first bit in the first data, perform a first flipping operation to the first data to obtain a second data including the bits, and store the second data to the memory device.