Memory Bit Inversion Scheme for Bad Cell Read Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Manufacturing variations in memory cells, particularly in electrically rewritable memories like MRAM and ReRAM, lead to issues with data reading and writing due to inconsistent resistance states, resulting in incorrect data retrieval and the need for time-consuming self-referencing reading techniques.
Innovation Solution
A memory system and method utilizing redundancy coding and decoding circuits, inverter circuits, selectors, comparators, and write control circuits to manage data writing and reading by inverting bit values and using comparison signals to ensure accurate data storage and retrieval, even with bad memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-referencing reading is used to handle bad memory cells, then reliability of data reading is improved, but access time increases due to requiring two readings and two writings
Solution Approach 1:
The patent applies preliminary action by pre-calculating inverted data before the write operation. The inverter circuit generates the inverted data in advance, and the selector circuit chooses between original and inverted data based on predicted bad memory cell locations. This eliminates the need for post-write verification readings, reducing access time while maintaining reliability.
Solution Approach 2:
The system uses self-service by having the memory controller itself determine which data version (original or inverted) to write, based on knowledge of bad memory cell locations. This self-determination eliminates the need for the memory cell to perform self-verification through repeated read-write cycles as in self-referencing reading.
2Manufacturing precision
If redundancy coding is performed to correct bad memory cells, then manufacturing precision tolerance is improved, but device complexity increases due to additional circuits
Solution Approach 1:
The patent applies local quality by selectively inverting data only for specific memory cells known to be bad, rather than applying redundancy coding to all memory cells. The selector circuit chooses between original and inverted data on a per-cell basis, adding minimal complexity only where needed to handle manufacturing variations.
Solution Approach 2:
The system changes the data parameter (inversion state) based on the characteristics of individual memory cells. By inverting bits in predetermined positions corresponding to bad memory cells, the system adapts to manufacturing variations without requiring complex redundancy coding circuits for the entire memory array.
Data Source
AI summary
A memory system has a redundancy coding circuit that performs redundancy coding process for write data, an inverter circuit which inverts values of individual bits of the data that has resulted from the redundancy coding process, a selector which selects the data that has resulted from the redundancy coding process or data that has been inverted by the inverter circuit based on a selecting signal, a memory which stores the selected data, a comparator which compares data read from the memory with the selected data and outputs a comparison result, a write control circuit which generates the selecting signal based on the comparison results, and a redundancy decoding circuit that performs a redundancy decoding process for data read from the memory to output the processed data.