Semiconductor Memory Bit Line Amplitude Control
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Solution Overview
Problem
As semiconductor memory devices scale, variations in transistor element characteristics lead to increased cell current variations, resulting in significant bit line amplitude and delay time distributions, which hinder low power consumption and operating speed, especially when power supply voltage is reduced.
Innovation Solution
Incorporating bit line limiters that monitor and limit the amplitude of bit lines to prevent excessive power consumption by cutting off the current path to the ground power supply voltage when sufficient amplitude is reached, thereby reducing unnecessary cell current flow and maintaining operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply voltage is reduced to achieve low power consumption, then power consumption decreases, but bit line amplitude becomes insufficient and operating speed deteriorates
Solution Approach 1:
The patent dynamically changes the power supply voltage parameter based on bit line amplitude conditions. When bit line amplitude is insufficient, the power supply voltage is increased to ensure proper operation. When amplitude is sufficient, voltage is reduced to minimize power consumption. This dynamic parameter adjustment resolves the contradiction between low power consumption and maintaining operating speed.
Solution Approach 2:
The invention introduces dynamic control of power supply voltage rather than using a fixed voltage level. The power supply voltage is adjusted in real-time based on the monitored bit line amplitude, allowing the system to adapt between power-saving mode and performance mode, thus resolving the static contradiction between power consumption and operating speed.
2Use of energy by moving object
If power supply voltage is reduced to achieve low power consumption, then power consumption decreases, but bit line delay time distribution increases
Solution Approach 1:
The patent dynamically adjusts the power supply voltage parameter based on bit line amplitude conditions. When delay time becomes excessive due to low voltage, the system increases voltage to restore timing characteristics. This dynamic parameter change resolves the contradiction between power consumption and bit line delay time.
3Quantity of substance
If transistor scaling is continued to increase integration density, then device density increases, but element characteristic variations increase
Solution Approach 1:
The patent implements a feedback mechanism that monitors bit line amplitude and uses this information to adjust power supply voltage. This feedback loop compensates for variations in transistor characteristics caused by scaling, ensuring consistent operation across devices with different characteristics and thereby improving reliability despite continued scaling.
4Reliability
If bit line amplitude is increased to ensure sufficient signal level, then signal reliability improves, but power consumption increases
Solution Approach 1:
The patent uses periodic monitoring of bit line amplitude and adjusts power supply voltage accordingly. The system alternates between high voltage (when amplitude is insufficient) and low voltage (when amplitude is sufficient), creating a periodic action pattern that optimizes the balance between signal reliability and power consumption.
Solution Approach 2:
The invention dynamically changes the power supply voltage parameter based on real-time bit line amplitude measurements. When amplitude reaches sufficient levels, voltage is reduced to minimize power consumption while maintaining adequate signal levels, thus resolving the contradiction between signal reliability and power consumption.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of memory cells each of which is arranged at the intersection position between a pair of complementary bit lines and a word line, and stores data between a first power supply voltage applied to a first node and a voltage applied to a virtual ground node, and a control circuit which changes the amount of current of the pair of bit lines in accordance with the amplitude of the pair of bit lines for each column in a memory macro, that is formed by arranging the plurality of memory cells in a matrix, in the data read operation of each of the plurality of memory cells.