Semiconductor Memory Bit Line Charge Control for Verify Accuracy
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Solution Overview
Problem
In NAND type flash memory, the miniaturization of memory cells leads to an adjacent NAND channel effect, where a memory cell's threshold value appears high due to channel potential interference, causing erroneous successful verify operations and read defects, as the bit line is not fully locked out during read operations.
Innovation Solution
Implementing a system where the bit line connected to a memory cell with an unsuccessful verify result is set to a high voltage without being locked out, preventing the adjacent NAND channel effect from influencing the verify operation and ensuring accurate threshold value assessment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase storage density, then storage capacity is improved, but adjacent NAND channel effect occurs causing measurement precision degradation
Solution Approach 1:
The patent applies preliminary anti-action by preemptively charging the bit line to a high voltage level (e.g., 0V or positive voltage) before the verify operation begins. This pre-charging action counteracts the adjacent NAND channel effect that would otherwise cause the threshold value to appear artificially high, thereby preventing measurement precision degradation while maintaining miniaturized memory cell structures for high storage density.
2Use of energy by moving object
If bit line is locked out during verify operation to reduce current consumption, then energy efficiency is improved, but adjacent NAND channel effect causes erroneous verify results
Solution Approach 1:
The patent implements preliminary action by charging the bit line to a high voltage level before the verify operation starts and maintaining this charge throughout the verify process. This pre-established voltage state ensures that the memory cell threshold value is accurately assessed without interference from adjacent channel effects, while the bit line remains locked out to other operations to minimize current consumption, thus achieving both energy efficiency and verify operation accuracy.
3Speed
If verify operation is performed without bit line charge maintenance, then operation speed is improved, but threshold value determination becomes inaccurate due to channel effects
Solution Approach 1:
The patent applies continuity of useful action by maintaining the bit line charge at a high voltage level continuously throughout the entire verify operation duration. This continuous voltage maintenance ensures that the threshold value determination remains accurate despite the presence of adjacent NAND channel effects, while the verify operation proceeds without interruption or additional charging cycles, thereby preserving operation speed.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of memory cells in which data can be rewritable, a plurality of bit lines connected to the plurality of memory cells, and a plurality of sense circuits that are connected to the plurality of bit lines, respectively, sense data written in the memory cells to perform a verify operation with the bit lines charged to first potentials, and charge a bit line, which is connected to a memory cell determined to be defective as a result of the verify operation, to the first potential in the verify operation.