Semiconductor Memory Bit Line Voltage Clamp Circuit
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Solution Overview
Problem
Existing semiconductor memory devices using variable-resistance elements face challenges in maintaining accurate read voltage during data retrieval, particularly due to power supply noise, which affects the reliability of data reading in memories like MRAM, ReRAM, and PCRAM.
Innovation Solution
The semiconductor memory device incorporates a voltage clamp circuit with MOSFETs that clamp the bit line to a predetermined read voltage and utilize gate capacitance as stabilizing capacitance to maintain a constant read voltage, even in the presence of power supply noise, by activating and deactivating specific MOSFETs based on the sense amplifier's status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a voltage clamp circuit with MOSFETs is used to maintain constant read voltage, then reading accuracy is improved, but device complexity increases
Solution Approach 1:
The voltage clamp circuit merges multiple MOSFETs (first MOSFET for clamping, second and third MOSFETs for capacitance control) into a single integrated structure that simultaneously performs voltage clamping and noise stabilization functions, resolving the contradiction by combining multiple functions into one device unit
Solution Approach 2:
The first MOSFET serves multiple functions: it acts as a voltage clamp element to maintain constant read voltage, and its gate capacitance simultaneously serves as stabilizing capacitance to suppress power supply noise, thereby improving reading accuracy without proportionally increasing device complexity
2Object-affected harmful factors
If gate capacitance of MOSFETs is used as stabilizing capacitance, then power supply noise suppression is improved, but control complexity increases
Solution Approach 1:
The second and third MOSFETs dynamically control the amount of gate capacitance from the first MOSFET that is utilized for noise suppression, allowing the system to adaptively adjust stabilization strength based on operating conditions, thereby improving noise suppression while maintaining manageable control complexity through automated switching
Solution Approach 2:
The control circuit monitors the operating state and automatically adjusts the switching states of the second and third MOSFETs to optimize the use of gate capacitance for noise suppression, implementing a feedback mechanism that resolves the contradiction by automating the control process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures highly accurate data reading by maintaining a constant read voltage, reducing the impact of power supply noise and enhancing the reliability of data retrieval, while also increasing the stabilizing capacitance to further mitigate noise effects.
Implementation Method 1
utilize gate capacitance as stabilizing capacitance to maintain a constant read voltage
Data Source
AI summary
A semiconductor memory device includes a memory cell having a resistance which differs based on stored data, a bit line connected to the memory cell, a first MOSFET which clamps the bit line to a read voltage when reading data, a sense amplifier which detects the stored data in the memory cell based on a current flowing through the bit line, a first switch element which connects the sense amplifier to a drain of the first MOSFET, a second switch element which connects a source of the first MOSFET to the bit line, a third switch element which connects the drain of the first MOSFET to a ground terminal, and a fourth switch element which connects the source of the first MOSFET to a ground terminal.