Nonvolatile Memory Bit Line Development Time Control
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in accurately controlling bit line development time across varying temperatures, leading to potential operation errors during read and verify operations.
Innovation Solution
The implementation of control logic that adjusts bit line development time based on temperature-dependent reference clock signals and temperature compensation pulse signals, ensuring optimal operation by varying frequencies and pulse widths according to temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed bit line development time is used across all temperatures, then the device operation is simple, but operation errors occur during read and verify operations at varying temperatures
Solution Approach 1:
The patent applies dynamics by making the bit line development time variable rather than fixed. The control logic dynamically adjusts the bit line development time based on temperature conditions, switching between different time values (first bit line development time at first temperature, second bit line development time at second temperature) to maintain reliable operation across varying thermal environments
Solution Approach 2:
The patent changes the parameter of bit line development time based on temperature. The control logic monitors temperature and adjusts the bit line development time parameter accordingly, using a first time value at lower temperatures and a second time value at higher temperatures, thereby adapting the operational parameters to thermal conditions to prevent operation errors
2Speed
If the bit line development time is shortened at higher temperatures, then operation speed increases, but timing precision requirements increase
Solution Approach 1:
The patent makes the bit line development time dynamic by adjusting it according to temperature. At higher temperatures where speed is critical, the second (shorter) bit line development time is applied to increase operation speed, while at lower temperatures the first (longer) time is used to maintain timing margins, thus dynamically optimizing the speed-time tradeoff based on thermal conditions
Data Source
AI summary
A nonvolatile memory device includes a memory cell, a bit line, a page buffer, and a control logic. The page buffer is connected to the memory cell through the bit line and the page buffer is configured to precharge the bit line to perform a desired operation. The desired operation may be one of a read operation and a verify operation. The control logic is configured to control bit line development time differently according to a temperature after precharging the bit line during the desired operation. The control logic is configured to determine the bit line development time according to a period of a reference clock signal that includes a different frequency depending on the temperature and/or a temperature compensation pulse signal including a pulse width that varies based on the temperature.