Memory Device Bit Line Discharge Timing for Programming Speed
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Solution Overview
Problem
Current memory devices face inefficiencies in programming operations due to fixed voltage application methods, which do not account for varying target program states of memory cells, leading to suboptimal performance and longer programming times.
Innovation Solution
A method and memory device configuration that apply program enable voltages to bit lines at different times and levels based on the target program states of memory cells, incorporating a bit line pre-charge and discharge operation controlled by a control logic to optimize programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed voltage application method is used for programming memory cells, then device complexity is reduced, but programming time increases and programming performance deteriorates
Solution Approach 1:
The patent segments the programming operation by dividing memory cells into different groups based on their target program states. Each group receives tailored voltage application timing, with some bit lines receiving program enable voltages at different times than others. This segmentation allows optimized programming speed for each group while maintaining manageable control logic through systematic classification.
Solution Approach 2:
The patent implements dynamic voltage application by adjusting the timing of program enable voltages applied to different bit lines based on target program states. The control logic dynamically determines when to apply voltages to each bit line, creating a time-varying programming scheme that improves overall programming speed without requiring complete redesign of the control system.
2Productivity
If uniform voltage application timing is used for all bit lines, then control logic is simplified, but programming efficiency decreases due to inability to account for varying target states
Solution Approach 1:
The patent applies preliminary action by performing a bit line pre-charge operation before the actual programming operation. This pre-charge step prepares all bit lines uniformly with a predetermined voltage level, simplifying the initial state for all subsequent programming operations. The pre-charge is performed once for all bit lines, maintaining operational simplicity while enabling efficient differentiated programming that follows.
Solution Approach 2:
The patent applies local quality by providing different voltage application timing to different bit lines based on their specific target program states. Each bit line receives customized programming timing locally, while the overall system maintains a unified control structure. This allows programming efficiency to be optimized for each local case without completely complicating the global control operation.
3Manufacturing precision
If bit line discharge operation is performed without pre-charge, then operation steps are reduced, but programming accuracy deteriorates due to inconsistent voltage levels
Solution Approach 1:
The patent applies beforehand cushioning through the bit line pre-charge operation that prepares voltage levels before programming begins. This pre-charge step acts as a cushioning measure that ensures all bit lines start from a known, consistent voltage state, preventing potential programming errors that could arise from inconsistent initial conditions. The pre-charge cushions against variability and ensures programming precision without adding excessive complexity.
Data Source
AI summary
A memory device having an improved program performance includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to program each of the plurality of memory cells to a target program state among a plurality of program states. The control logic is configured to control the peripheral circuit to apply a program voltage to a word line that is coupled to the plurality of memory cells and perform a bit line discharge operation of applying program enable voltages to a plurality of bit lines that is coupled to the plurality of memory cells while the program voltage is applied to the word line. Timings for applying the program enable voltages to the plurality of bit lines are determined based on the corresponding target program states.