Semiconductor Memory Bit Line Potential Control via Feedback
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Solution Overview
Problem
Conventional techniques for controlling bit line potential in semiconductor memory devices often result in excessive stepping down, leading to erroneous operations, reduced static noise margin (SNM), and slower operation speeds due to increased drive capability variations and pulse signal deformations.
Innovation Solution
The implementation of semiconductor memory devices with a potential control technique using transistors and capacitors to regulate bit line potential, reducing excessive stepping down and improving SNM, while allowing for higher-speed operations by stepping down the bit line potential with reduced amplitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the drive capability of the NMOS transistor is increased to step down the bit line potential, then the bit line potential is stepped down more effectively, but the possibility of erroneous write operation increases due to excessive stepping down
Solution Approach 1:
The patent implements a feedback mechanism where the bit line potential is monitored and fed back to control the NMOS transistor gate. When the bit line potential reaches a predetermined threshold, the feedback signal turns off the NMOS transistor, preventing excessive stepping down and erroneous write operations while maintaining effective potential control.
Solution Approach 2:
The patent introduces a feedback control circuit as an intermediary between the bit line and the NMOS transistor. This intermediary monitors the bit line potential and mediates the control signal to the NMOS transistor, ensuring the potential is stepped down to the appropriate level without causing erroneous operations.
2Reliability
If the bit line potential is stepped down to improve SNM, then the static noise margin is improved, but the drive capability of the access transistor is reduced, slowing down the operation
Solution Approach 1:
The patent employs periodic action by using a sense amplifier that operates in phases: first, the bit line potential is stepped down during the precharge phase, then during the read phase, the sense amplifier activates to detect the potential difference and restore the bit line potential. This periodic operation allows SNM improvement while maintaining high-speed read operations.
3Reliability
If the pulse signal width is increased to ensure proper transistor control, then the transistor control is more reliable, but the pulse signal deformation increases, causing excessive bit line potential stepping down
Solution Approach 1:
The feedback control circuit monitors the actual bit line potential and adjusts the pulse signal width dynamically. When the bit line potential reaches the target level, the feedback signal terminates the pulse, preventing signal deformation and excessive stepping down while ensuring reliable transistor control throughout the operation.
4Productivity
If the decoder circuit amplitude is reduced to increase speed and reduce power, then the operation speed increases and power consumption decreases, but the precharge time of the NMOS transistor increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a elevated potential level before the read operation begins. This preliminary action reduces the precharge time required during normal operation, allowing the decoder to use reduced amplitude signals for speed and power optimization without sacrificing operational timing.
Data Source
AI summary
A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses.