Semiconductor Memory Bit Line Precharge for Current Stability
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Solution Overview
Problem
The operating characteristics of semiconductor memory cells are deteriorated due to changes in memory block structure or reduction in cell size, leading to insufficient current for improved input and output performance.
Innovation Solution
A semiconductor memory apparatus with memory cells coupled between a bit line and a source line, operating in response to word line voltages, and a peripheral circuit that applies a precharge voltage to the bit line when adjacent word lines are set to a floating state, ensuring stable current flow and preventing carrier velocity saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced or memory block structure is changed to increase storage capacity, then storage density is improved, but operating characteristics and current flow are deteriorated
Solution Approach 1:
The patent changes the voltage parameter of the bit line by applying a precharge voltage (Vbl_pre) before the read operation. This parameter change ensures sufficient current flow through the memory cell transistor even when the cell size is reduced, thereby maintaining reliable operating characteristics while enabling higher storage density.
Solution Approach 2:
The patent performs a preliminary action by precharging the bit line to a specific voltage level before the actual read operation begins. This preliminary voltage application ensures that when the read operation starts, the bit line is already in the optimal state to drive sufficient current through the scaled-down memory cell, preventing operating characteristic deterioration.
2Area of moving object
If memory cell size is reduced to increase integration density, then storage density is improved, but current flow and input/output performance are insufficient
Solution Approach 1:
The patent compensates for the reduced current flow capability of smaller memory cells by changing the bit line voltage parameter. By applying a precharge voltage that ensures sufficient voltage headroom, the system maintains adequate current flow (Ion) through the reduced-size memory cell transistor, thus preserving input/output performance despite smaller cell area.
3Device complexity
If word lines are kept at fixed voltage levels during read operation, then circuit control is simplified, but carrier velocity saturation occurs and hot carrier generation increases
Solution Approach 1:
Instead of keeping unselected word lines at a fixed high voltage level (conventional approach), the patent inverts the approach by setting them to a floating state (high-impedance state). This inversion prevents carrier velocity saturation and hot carrier generation in unselected memory cells while still enabling proper read operation in the selected cell, and it simplifies control circuitry by removing the need for continuous voltage driving on unselected word lines.
Data Source
AI summary
A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.