Memory Architecture Bit Line Segmentation for Write Speed
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Solution Overview
Problem
In memory arrays, the large effective capacitance of global bit lines and local bit lines degrades the writing speed and increases power consumption due to the electrical shorting of global bit lines with multiple pairs of local bit lines, affecting the memory cells being written.
Innovation Solution
Isolating the local bit line associated with the memory cell to be written from other local bit lines, reducing the effective capacitance and using a negative boost circuit to pre-charge and pull down the bit lines efficiently, thereby improving write speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the global bit line is electrically shorted with multiple pairs of upper and lower local bit lines, then the data can be written to multiple memory cells simultaneously, but the effective capacitance increases and degrades writing speed
Solution Approach 1:
The patent divides the global bit line into multiple independent segments, where each segment is electrically isolated and can be independently controlled. This segmentation allows selective activation of only the bit line segment corresponding to the target memory cell, preventing capacitive loading from other segments while maintaining the ability to address multiple cells through different segments.
Solution Approach 2:
The patent extracts and removes the harmful capacitive coupling between global bit line segments by introducing isolation mechanisms. Specifically, it uses transmission gates controlled by word lines to disconnect unused segments from the global bit line, effectively removing the parasitic capacitance that would otherwise degrade write speed.
2Productivity
If the global bit line is shorted with multiple pairs of local bit lines, then data can be transferred in parallel, but power consumption increases due to charging large capacitance
Solution Approach 1:
By segmenting the global bit line into isolated sections controlled by different word lines, the patent enables selective activation of only the necessary bit line segments during each write operation. This reduces the total capacitance that needs to be charged and discharged, thereby lowering power consumption while maintaining parallel data transfer capability across different segments.
Solution Approach 2:
The patent employs precharge circuits that prepare the bit lines in advance by setting them to a predetermined voltage state before the actual write operation. This preliminary action reduces the voltage swing required during writing, thereby reducing the energy consumed in charging and discharging the bit line capacitance.
3Device complexity
If all local bit lines are coupled together with the global bit line, then the circuit structure is simplified, but the memory cell to be written is affected by large effective capacitance
Solution Approach 1:
The patent introduces segmentation into the previously unified global bit line structure by dividing it into multiple electrically isolated segments. Each segment is controlled independently through word line-dependent transmission gates, maintaining relatively simple circuitry while eliminating the harmful capacitive coupling that degraded write speed.
Solution Approach 2:
The patent introduces transmission gates controlled by word lines as intermediary elements between the global bit line segments and local bit lines. These intermediaries act as switches that connect or disconnect segments based on the target memory cell location, providing a simple yet effective mechanism to isolate capacitance without complicating the overall circuit structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the effective capacitance seen by the memory cell, enhancing write speed and minimizing power consumption by half compared to existing methods, allowing for smaller circuit and die sizes while maintaining performance.
Implementation Method 1
the memory cell to be written is affected by an effective capacitance of the global bit line and of the plurality of pairs of upper and lower local bit lines
Data Source
AI summary
A write circuit in a memory array includes a global data line, a switching circuit, and a first local data line coupled with the switching circuit and with a first plurality of memory cells. The global data line is configured to receive data to be written to the memory cell from outside of the memory array. The switching circuit is configured to electrically couple the global data line with the first local data line to transfer the data to be written to a memory cell of the first plurality of memory cells to the first local data line. The memory cell of the first plurality of memory cells is configured to receive data on the first local data line.