Semiconductor Memory Bit Line Select Transistor Segmentation
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Solution Overview
Problem
NAND flash memory devices face challenges in reducing chip size while maintaining read margin due to the need for high-voltage transistors and long interconnects, which increase chip size and decrease read margin performance.
Innovation Solution
The arrangement of first and second bit line select transistors on the same side as the sense amplifier, allowing for the use of low-voltage transistors and reducing interconnect length, thereby minimizing chip size and maintaining read margin by optimizing the placement and voltage generation circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage transistors are used for bit line select transistors to handle erase voltage, then the transistor can withstand high voltage, but the transistor size increases resulting in larger chip size
Solution Approach 1:
The bit line select transistors are segmented into two groups: first bit line select transistors connected to the sense amplifier side and second bit line select transistors connected to the opposite side. This segmentation allows different voltage handling requirements to be met in different regions, enabling the use of low-voltage transistors in most areas while maintaining high-voltage capability where needed.
Solution Approach 2:
A voltage generation circuit is introduced as an intermediary component that generates the high voltage (Vera) needed for erase operations. This circuit is connected to the second bit line select transistors through a transformer, allowing high-voltage transistors to be replaced with low-voltage transistors while still achieving high-voltage operation through the intermediary voltage generation mechanism.
2Ease of operation
If the voltage generation circuit is placed on the side opposite to the sense amplifier to drive second bit line select transistors, then the transistors can be properly driven, but the interconnect length increases resulting in larger chip size
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by placing the voltage generation circuit and transformer in a different spatial dimension relative to the bit line select transistors. This dimensional reorganization allows short interconnects to achieve the same electrical connection that would otherwise require long horizontal traces, reducing the interconnect length and chip size.
3Area of stationary object
If micropatterning is advanced to reduce interconnect pitch, then the chip size decreases, but the breakdown voltage between interconnects becomes difficult to maintain
Solution Approach 1:
The patent applies different quality requirements to different regions: low-voltage transistors with optimized dimensions are used in regions where high breakdown voltage is not critical, while the voltage generation circuit and transformer are positioned in regions requiring high voltage handling. This local differentiation allows micropatterning to be advanced in low-voltage regions without compromising overall breakdown voltage reliability.
Data Source
AI summary
According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.