Semiconductor Memory Bit Line Selecting Circuit Size Reduction
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Solution Overview
Problem
The size of semiconductor memory devices is limited by the large number of high voltage transistors required for bit line selecting circuits, which are necessary for erase operations, making it difficult to reduce the device size.
Innovation Solution
The implementation of a semiconductor memory device with a reduced number of high voltage transistors by using a bit line selecting circuit with low voltage transistors in the cell area and a high voltage switching circuit in the surrounding area, allowing for a smaller device size while maintaining operational functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage transistors are used in the bit line selecting circuit for erase operations, then the erase operation can be performed effectively, but the device size increases
Solution Approach 1:
The patent divides the transistor circuit into two distinct segments: low voltage transistors (first through fourth N-MOS transistors) for bit line selection in the cell area, and a separate high voltage transistor (fifth N-MOS transistor) for erase operations in the surrounding circuit area. This segmentation allows each transistor type to be optimized for its specific function, reducing the overall device size while maintaining erase operation effectiveness.
Solution Approach 2:
The patent applies different voltage characteristics to different regions of the device. Low voltage transistors are used in the cell area where bit line selection is needed, while a high voltage transistor is specifically placed in the surrounding circuit area where erase operations are performed. This local differentiation of voltage quality allows the device to perform both functions with minimal transistor count and reduced size.
2Reliability
If the number of high voltage transistors is increased to ensure erase operation, then erase reliability is improved, but the manufacturing complexity increases
Solution Approach 1:
The circuit is segmented into low voltage and high voltage transistor regions, with only one high voltage transistor (the fifth N-MOS transistor) required for erase operations. This segmentation simplifies manufacturing by reducing the number of complex high voltage transistors that need to be fabricated, while still ensuring erase operation reliability through the dedicated high voltage transistor in the surrounding circuit area.
3Area of stationary object
If low voltage transistors are used in the bit line selecting circuit, then the device size is reduced, but the high voltage protection of surrounding circuits is compromised
Solution Approach 1:
The patent implements local quality by placing low voltage transistors in the cell area for bit line selection while positioning a high voltage transistor (the fifth N-MOS transistor) specifically in the surrounding circuit area. This high voltage transistor acts as a protective element that shields surrounding circuits from high voltage during erase operations, while the low voltage transistors in the cell area maintain reduced device size.
Solution Approach 2:
The fifth N-MOS transistor in the surrounding circuit area serves as an intermediary protective element between the high voltage erase operation and the surrounding circuits. It mediates the high voltage exposure, allowing low voltage transistors to be used in the cell area for size reduction while still providing high voltage protection to the surrounding circuit area.
Data Source
AI summary
A semiconductor memory having a plurality of memory cells coupled to bit lines includes a bit line selecting circuit, a latch circuit, and a switching circuit. The bit line selecting circuit is disposed in a cell area where the memory cells are formed. The bit line selecting circuit is configured to select one of the bit lines in response to a first control signal. The latch circuit is disposed in a surrounding circuit area. The latch circuit is configured to perform a program operation or a read operation on the memory cells corresponding to the bit line selected by the bit line selecting circuit. The switching circuit is disposed in the surrounding circuit area, and is coupled between the bit line selecting circuit and the latch circuit. The switching circuit is configured to switch between the bit line selecting circuit and the latch circuit in response to a second control signal.