Semiconductor Memory Bit Line Selection Transistor Configuration
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Solution Overview
Problem
NAND type flash memory devices face challenges in reducing interference between adjoining cells and expanding chip area, particularly due to limitations in programming systems like Even/Odd and All Bit Line systems.
Innovation Solution
A semiconductor memory device design that includes a memory cell array with plural memory cells connected to word lines and bit lines in a matrix form, utilizing sense amplifiers and selection transistors to connect bit lines to sense amplifiers, allowing for both even/odd and pair programming while minimizing chip area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the Even/Odd programming system is used to reduce interference between adjoining cells, then programming precision is improved, but productivity deteriorates because cells cannot be programmed simultaneously
Solution Approach 1:
The patent applies dynamics by making the bit line connection configuration changeable through selection transistors. The system can dynamically switch between connecting adjacent bit lines to the same sense amplifier (for simultaneous programming) and connecting alternate bit lines to different sense amplifiers (for reduced interference during verification), thereby resolving the contradiction between programming speed and precision
Solution Approach 2:
The patent changes the connection parameter between bit lines and sense amplifiers based on the operation mode. During programming, adjacent bit lines are connected to the same sense amplifier to enable simultaneous operation. During verification, alternate bit lines are connected to different sense amplifiers to reduce capacitive coupling interference, thus achieving both high productivity and high precision
2Productivity
If the All Bit Line system is used to enable simultaneous programming of all cells, then productivity is improved, but device complexity increases due to requiring a sense amplifier for each bit line
Solution Approach 1:
The patent makes each sense amplifier multi-functional by enabling it to serve multiple bit lines through selection transistors. A single sense amplifier can simultaneously handle programming for adjacent bit lines while being selectively connected to alternate bit lines for verification, thereby achieving high-speed programming without requiring a sense amplifier for every bit line
Solution Approach 2:
The selection transistors act as intermediaries between bit lines and sense amplifiers. These intermediaries enable flexible connection configurations that allow a reduced number of sense amplifiers to effectively serve multiple bit lines, thus reducing device complexity while maintaining high productivity
3Productivity
If sense amplifiers are connected to each bit line to enable all bit line programming, then productivity is improved, but area of the device increases
Solution Approach 1:
The patent merges the functions of multiple bit lines to a single sense amplifier through selection transistors. By combining the verification function of alternate bit lines to the same sense amplifier, the chip area is reduced while simultaneous programming capability is maintained through the selective connection mechanism
Data Source
AI summary
A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier.