Semiconductor Memory Bit Line Data Shifting via Switched Sense Amplifiers
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in efficiently shifting data from an arbitrary row address to a different row address, limiting their ability to optimize data storage and refresh operations, especially in graphic memories and large data storage scenarios.
Innovation Solution
A semiconductor memory device with a plurality of memory cell blocks and sense amplifier blocks, where switches connect bit lines between adjacent memory cell blocks, allowing data to be shifted by activating specific sense amplifier circuits and switches in response to shift signals, enabling data relocation between memory cell blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is stored in conventional semiconductor memory devices with fixed bit line connections, then the device structure is simple and reliable, but data cannot be efficiently shifted between different row addresses
Solution Approach 1:
The patent applies the dynamics principle by making the bit line connections dynamic rather than fixed. Switches are introduced to enable configurable connections between bit lines of adjacent memory cell blocks, allowing the system to adapt its topology based on operational needs such as data shifting or normal read/write operations.
Solution Approach 2:
The patent implements universality by designing the memory device to perform multiple functions: normal read/write operations and data shifting operations. The same basic memory structure supports both conventional operations and advanced data relocation capabilities through the controlled activation of switches and sense amplifiers.
2Productivity
If switches are added to enable data shifting between memory cell blocks, then data can be relocated efficiently, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory device into multiple independent memory cell blocks (MCB1, MCB2, MCB3, MCB4), each with its own sense amplifier blocks. This modular structure allows data shifting to be implemented locally between blocks without requiring complete restructuring of the entire memory system.
Solution Approach 2:
The patent uses sense amplifier blocks as intermediaries to facilitate data transfer between memory cell blocks. The sense amplifiers act as mediator circuits that can detect and transfer data signals between adjacent blocks through shared bit lines, enabling efficient data shifting without direct complex switching between all blocks.
3Adaptability or versatility
If bit lines of adjacent memory cell blocks are connected through sense amplifier blocks, then data can be shifted between blocks, but the connection flexibility is limited to specific configurations
Solution Approach 1:
The patent merges the functions of sense amplifiers and switching mechanisms into integrated sense amplifier blocks positioned between memory cell blocks. This combination allows the same circuitry to perform both data sensing and data transfer functions, reducing the need for separate dedicated switching components and simplifying the overall control logic.
Data Source
AI summary
Provided is a semiconductor memory device having connected bit lines and a data shifting method thereof. An embodiment of the semiconductor memory device includes a plurality of memory cell blocks each including a plurality of bit lines and a plurality of word lines, a plurality of sense amplifier blocks respectively disposed between the memory cell blocks, wherein each sense amplifier block includes a plurality of sense amplifier circuits corresponding to the bit lines, and a plurality of switches. The switches connect bit lines not sharing a sense amplifier block among bit lines of adjacent memory cell blocks between which the sense amplifier block is disposed, in response to a shift signal. Therefore, in the semiconductor memory device and the data shift method thereof, it is possible to easily shift data stored in memory cells connected to an arbitrary word line to memory cells connected to another arbitrary word line.