Memory Device Bit Line Vertical Stacking for Breakdown Prevention
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Solution Overview
Problem
In memory devices, particularly flash memory, the close proximity of bit lines and multiplexers leads to breakdown issues during erase operations due to high voltage differences, causing undesired couplings to break down.
Innovation Solution
Implementing a design where bit lines are arranged at multiple vertical levels, with multiplexers and sensing devices connected at different vertical levels to reduce electric field interference and prevent breakdowns, using separate wiring layers for each level to manage voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit lines and multiplexers are placed at the same vertical level to simplify wiring, then device complexity is reduced, but electric field stress causes breakdown during high-voltage erase operations
Solution Approach 1:
The patent applies vertical stacking to separate bit lines and multiplexers into different vertical levels (first level and second level). This dimensional separation reduces electric field stress between adjacent lines during high-voltage erase operations while maintaining compact device footprint. The multiplexer is positioned at a second vertical level above the bit lines at the first vertical level, creating vertical spacing that prevents breakdown.
2Productivity
If process improvement increases feature density, then productivity is improved, but coupling distance between bit lines and multiplexers decreases causing breakdown
Solution Approach 1:
By transitioning from planar coupling to vertical stacking, the patent maintains small horizontal distances for high feature density while creating vertical separation for reliability. The bit lines and multiplexers are coupled through vertical connections rather than horizontal proximity, enabling dense packaging without sacrificing coupling stability during high-voltage operations.
Solution Approach 2:
The patent segments the coupling path into vertical components: bit lines at a first vertical level, intermediate coupling structures, and multiplexers at a second vertical level. This segmentation allows independent optimization of each layer's dimensions and materials, achieving both high density and high reliability.
3Power
If high voltage is applied to bit lines during erase operations, then erase capability is improved, but electric field stress causes coupling breakdown
Solution Approach 1:
The vertical stacking architecture separates high-voltage bit lines at the first vertical level from low-voltage multiplexers at the second vertical level. This spatial separation in the vertical dimension reduces electric field stress at coupling interfaces during erase operations, enabling high-voltage erase capability without compromising coupling integrity.
Data Source
AI summary
A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.