Semiconductor Memory Bit Line Voltage Control

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Solution Overview

Problem

The increasing number of memory cells connected to one word line in semiconductor memory devices leads to varying program voltage levels across memory cells, resulting in wide threshold voltage distribution, which deteriorates program performance by prolonging the time required for program operations.

Innovation Solution

A semiconductor memory device and method that apply different bit line voltages based on the distance between the row decoder and memory cells during program operations, ensuring that each memory group receives a varying bit line voltage, thereby narrowing the threshold voltage distribution without compromising program performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of memory cells connected to one word line is increased, then the reliability of the semiconductor memory device is enhanced, but the threshold voltage distribution of the memory cells becomes wide

Engineering Contradiction:
Improvereliability of semiconductor memory deviceVSAvoidthreshold voltage distribution
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies different bit line voltage levels to different memory groups based on their distance from the row decoder. Memory groups closer to the row decoder receive one voltage level, while those farther away receive a different voltage level. This local differentiation compensates for the voltage drop along the word line, ensuring uniform threshold voltage distribution across all memory cells connected to the same word line, thereby resolving the contradiction between increased reliability and maintained manufacturing precision.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If additional program pulses are applied to increase the threshold voltage of memory cells far from the row decoder, then the threshold voltage distribution is improved, but the program operation time is prolonged

Engineering Contradiction:
Improvethreshold voltage distributionVSAvoidprogram operation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies different bit line voltage levels in advance during the program operation based on the memory group's distance from the row decoder. By pre-compensating for the expected voltage drop through appropriate voltage selection, the threshold voltage of memory cells far from the row decoder is adjusted more efficiently without requiring additional program pulses, thus improving threshold voltage distribution while maintaining program operation speed.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If different bit line voltage levels are applied to memory groups at different distances from the row decoder, then the threshold voltage distribution is narrowed, but the device complexity increases

Engineering Contradiction:
Improvethreshold voltage distributionVSAvoidbit line voltage supply circuit
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the memory array into multiple memory groups, where each group is associated with a specific bit line voltage level based on its distance from the row decoder. This segmentation allows the bit line voltage supply circuit to manage different voltage levels in an organized manner, applying appropriate voltages to specific memory groups without requiring complex individual control for each memory cell, thus narrowing threshold voltage distribution while controlling device complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9129682B2Semiconductor memory device and method of operating the same
Publication Date: 2015.09.08 SK HYNIX INC
  • US9129682B2 patent drawing
  • US9129682B2 patent drawing
  • US9129682B2 patent drawing

AI summary

In a semiconductor memory device and a method of operating the same, a memory block including memory cells is divided into memory groups. A level of bit line voltage applied to a bit line coupled to the memory cells included in each of the memory groups varies according to a distance between a row decoder and each memory groups during a program operation. Characteristics of the threshold voltage distribution of the memory cells in the semiconductor memory device may be improved without deteriorating performance of the program.