Semiconductor Memory Bit Line Voltage Isolation
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Solution Overview
Problem
As semiconductor memory devices become highly integrated, neighboring bit lines can become coupled, leading to parasitic capacitance and unintended current flow between bit lines, causing data read or write errors due to the increasing number of unit memory cells and bit lines in a small area.
Innovation Solution
The semiconductor memory device employs a method of applying different power-supply voltages to bit lines using first and second power-supply voltage circuits and address selection circuits to selectively couple these voltages to specific bit lines, preventing unintended current paths by generating a potential difference between neighboring bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of unit memory cells and bit lines is increased to achieve high integration, then storage capacity and device functionality are improved, but parasitic capacitance and unintended current flow between neighboring bit lines increase, causing data read/write errors
Solution Approach 1:
The patent applies different power-supply voltages to different bit lines based on their spatial locations. Specifically, first power-supply voltage is applied to first bit lines while second power-supply voltage is applied to second bit lines. This local differentiation creates potential differences that prevent unintended current flow between neighboring bit lines, thereby maintaining data read/write accuracy while supporting high integration
Solution Approach 2:
The patent segments the bit lines into multiple groups (first bit lines and second bit lines) and applies different power-supply voltages to each group. This segmentation approach divides the complex system into manageable parts with controlled electrical characteristics, preventing parasitic current paths while maintaining overall device functionality
2Area of stationary object
If neighboring bit lines are coupled to increase integration density, then device area efficiency is improved, but parasitic capacitance occurs leading to unintended current flow and data errors
Solution Approach 1:
The patent applies different power-supply voltages to different bit lines based on their spatial locations. Specifically, first power-supply voltage is applied to first bit lines while second power-supply voltage is applied to second bit lines. This local differentiation creates potential differences that prevent unintended current flow between neighboring bit lines, thereby maintaining data read/write accuracy while supporting high integration
Solution Approach 2:
The patent converts the potentially harmful effect of close spacing (which causes parasitic capacitance) into a beneficial effect by exploiting the resulting potential differences. By applying different voltages to neighboring bit lines, the patent uses the voltage difference to actively prevent parasitic current flow, turning a geometric constraint into an electrical advantage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively removes unexpected current paths between bit lines during manufacturing, preventing faulty operations and ensuring accurate data read/write operations by isolating and managing current flow through distinct power-supply voltages.
Implementation Method 1
applying different power-supply voltages to bit lines coupled to a cell array and removes a current path between bit lines unexpectedly formed
Data Source
AI summary
A semiconductor memory device includes a memory cell array configured to include a plurality of memory cells, a plurality of bit lines respectively coupled to the plurality of memory cells, a first power-supply voltage supplying circuit configured to provide a first power-supply voltage to the memory cell array through the plurality of bit lines, a second power-supply voltage supplying circuit configured to provide a second power-supply voltage to the memory cell array through the plurality of bit lines, a first address selection circuit configured to couple a bit line selected by a first selection address to the first power-supply voltage supplying circuit, and a second address selection circuit configured to couple a bit line selected by a second selection address to the second power-supply voltage supplying circuit.