Memory Device Bit Line Voltage Control for Read Disturb Reduction
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Solution Overview
Problem
Flash memory devices face reliability concerns due to drain read disturb, which occurs when the drain side voltage is too high during read operations, and as cells scale down and read windows narrow, setting appropriate drain voltage becomes critical for maintaining product functionality and reliability.
Innovation Solution
A memory device with a regulator and controllable current source is implemented to provide a bit line voltage and bias voltage to selected cells, conducting a controllable current until a cell current threshold is reached, thereby maintaining the bit line voltage and reducing read disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If drain side voltage is increased during read operation, then read speed is improved, but drain read disturb increases causing reliability degradation
Solution Approach 1:
The patent applies dynamics by making the bit line voltage dynamic rather than static. The voltage is adjusted in real-time based on the read operation progress and cell state, transitioning from a higher initial voltage to a lower final voltage. This dynamic adjustment allows the system to achieve fast read speed initially while preventing read disturb later, resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent changes the voltage parameter during the read operation. Specifically, the bit line voltage is changed from a higher level (e.g., VBL_HIGH) to a lower level (e.g., VBL_LOW) based on the read operation stage. This parameter change enables the system to optimize both read speed and reliability by using different voltage levels for different phases of the same operation.
2Measurement precision
If drain voltage is set high to improve read performance, then read window is improved, but read disturbance to neighboring cells increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a high voltage level before the actual read operation begins. This preliminary high voltage state helps establish a good read window and signal margin. Then, during the read operation, the voltage is reduced to prevent disturbance, thus achieving both good read window and minimal disturbance through sequential voltage management.
Solution Approach 2:
The patent uses periodic action by applying different voltage levels at different time periods during the read operation. The bit line voltage is set to a high level during the initial phase to establish read window, then switched to a low level during the verification phase to prevent disturbance. This time-based voltage switching resolves the contradiction between read window and read disturbance.
Data Source
AI summary
A memory device is provided. The memory device includes: a memory array having a plurality of cells; a regulator, coupled to the memory, the regulator being configured to provide a bit line voltage to a selected cell of the memory array and to provide a bias voltage; and a controllable current source, coupled to the memory array, the controllable current source being configured to conduct a controllable current in the controllable current source until a cell current of the selected cell reaches a threshold.