Semiconductor Memory Bit Line Voltage Control for Program Accuracy
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently controlling bit line voltages during program operations, particularly in performing auxiliary verify operations and maintaining optimal threshold voltage distribution for multi-level cells, which affects program speed and accuracy.
Innovation Solution
The semiconductor memory device incorporates a control logic system that manages bit line voltages by applying specific voltages to bit line connection transistors, using program inhibit, second program allowable, and first program allowable voltages based on threshold voltage states, allowing for precise control during main verify, first auxiliary verify, and second auxiliary verify operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform bit line voltage is applied to all memory cells during program operation, then the control circuit is simple, but the threshold voltage distribution width is large and program accuracy is reduced
Solution Approach 1:
The patent divides memory cells into multiple groups based on their threshold voltage characteristics (first group with threshold voltage ≤ first verify voltage, second group with threshold voltage > first verify voltage). Different bit line voltages are applied to different groups: first bit line voltage to the first group and second bit line voltage to the second group. This segmentation enables precise control of threshold voltage distribution while maintaining manageable control complexity through systematic classification.
Solution Approach 2:
The patent applies different bit line voltages to different memory cell groups based on their specific threshold voltage characteristics. The first bit line voltage is applied locally to memory cells in the first group, while the second bit line voltage is applied locally to memory cells in the second group. This local quality approach optimizes programming accuracy for each group while avoiding the need for complex uniform control across all cells.
2Measurement precision
If multiple bit line voltages are applied to different memory cell groups, then program accuracy is improved, but the control circuit complexity increases
Solution Approach 1:
The patent segments memory cells into distinct groups based on threshold voltage verification results and applies corresponding specific voltages to each group. This segmentation enables high program accuracy by tailoring voltages to cell characteristics while managing control circuit complexity through structured group management and systematic voltage assignment.
Solution Approach 2:
The patent changes the bit line voltage parameter based on memory cell group membership. The control circuit dynamically selects between first bit line voltage and second bit line voltage depending on which group the memory cell belongs to. This parameter change approach improves program accuracy by optimizing voltages for different cell characteristics while controlling circuit complexity through discrete, manageable voltage levels.
3Manufacturing precision
If auxiliary verify operations are performed with multiple voltage levels, then threshold voltage distribution is improved, but program operation time increases
Solution Approach 1:
The patent segments the verification process into multiple stages with different voltage levels (first auxiliary verify operation with first verify voltage, second auxiliary verify operation with second verify voltage, and main verify operation with third verify voltage). Memory cells are systematically evaluated at each stage and assigned to appropriate groups, enabling improved threshold voltage distribution through structured multi-level verification while managing operation time through efficient sequential processing.
Solution Approach 2:
The patent performs preliminary auxiliary verify operations before the main verify operation to pre-classify memory cells into appropriate groups. This preliminary action allows the main verify operation to proceed more efficiently with predetermined voltage assignments, improving threshold voltage distribution characteristic while minimizing overall operation time through advance preparation.
Data Source
AI summary
A page buffer of a semiconductor memory device includes a bit line connection transistor, an internal operation circuit, and a plurality of latch circuits. During a program operation of selected memory cells, a power voltage is applied to the bit line connection transistor to set a voltage of a bit line connected to memory cells having a threshold voltage greater than a main verify voltage as a program inhibit voltage. In addition, a second program allowable voltage less than the program inhibit voltage is applied to the bit line connection transistor. In addition, a first program allowable voltage less than the second program allowable voltage is applied to the gate of the bit line connection transistor.