Semiconductor Memory Bit Line Voltage Sequencing
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing the read operation efficiency due to the time required to determine whether the selected memory cell transistor is an on-cell or off-cell, particularly in charging the bit line to the appropriate voltage level, which affects the speed and accuracy of data retrieval.
Innovation Solution
The semiconductor memory device employs a control circuit that applies specific voltage sequences to the bit line and source line during the read operation, utilizing a threshold voltage sensing mechanism to quickly determine the state of the memory cell transistor, thereby optimizing the charging period and reducing the overall read operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the bit line is charged to the appropriate voltage level during read operation, then the accuracy of data retrieval is improved, but the time required for the read operation increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level before the actual read operation begins. The control circuit charges the bit line to a first voltage level in advance, then applies a second voltage level during the read operation. This preliminary preparation eliminates the need to charge the bit line during the critical read measurement phase, thereby reducing read operation time while maintaining accurate threshold voltage sensing.
Solution Approach 2:
The patent segments the voltage application process into distinct time periods: a first period for pre-charging the bit line to a first voltage level, and a second period for applying a second voltage level during the actual read operation. This temporal segmentation allows the system to prepare the bit line in advance without interfering with the precision measurement phase, resolving the contradiction between speed and accuracy.
2Productivity
If the bit line charging period is optimized to reduce read operation time, then productivity is improved, but the reliability of threshold voltage sensing may deteriorate
Solution Approach 1:
The control circuit performs preliminary charging of the bit line to a first voltage level before the threshold voltage sensing operation. This pre-charging ensures that the bit line is properly prepared and stabilized, eliminating the need for extended charging periods during the actual read operation. The reliability of threshold voltage sensing is maintained because the bit line reaches the required voltage level in advance, allowing sufficient time for stable sensing without compromising speed.
3Speed
If a higher voltage is applied to the bit line during the read operation, then the speed of data retrieval is improved, but the energy consumption increases
Solution Approach 1:
The patent employs periodic action by applying different voltage levels to the bit line at different time periods. During the first period, a first voltage level is applied for pre-charging. During the second period, a second voltage level (higher than the first) is applied during the actual read operation to enable faster electron tunneling and quicker data retrieval. This time-dependent voltage modulation achieves high-speed operation when needed while managing overall energy consumption through controlled, periodic voltage application rather than continuous high voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for faster and more accurate data retrieval by ensuring the bit line is charged to the correct voltage level quickly, shortening the read operation time and improving the efficiency of data access, especially in multi-page read operations.
Implementation Method 1
sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period
Data Source
AI summary
A semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation for reading read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage, higher than the first voltage, to the bit line, and also apply a third voltage, lower than the first voltage, to the source line in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.