Memory Bit Ordering with Matrix Decode Circuits to Reduce Latency
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Solution Overview
Problem
Memory devices without logic for ordering information contribute to increased latency and reduced throughput in arithmetic operations due to the need for processing resources to reorder and manipulate data before execution, which affects overall computing system performance.
Innovation Solution
Implementing an array of memory cells with a controller and column decode circuitry to order bits in a particular matrix configuration, allowing data to be sent and written in a predefined order via sense amplifiers to processing resources, reducing the need for reordering by the processing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory devices send data in arbitrary order without ordering logic, then device complexity is reduced, but processing resources require additional reordering steps increasing latency
Solution Approach 1:
The memory device performs preliminary ordering of data bits in a matrix configuration before data leaves the memory device. The column decode circuitry receives data from sense amplifiers and orders it according to a matrix configuration corresponding to the arithmetic operations, so that processing resources receive pre-ordered data and don't need to perform reordering steps
2Productivity
If memory devices implement ordering logic for data bits, then processing throughput is improved, but device complexity increases
Solution Approach 1:
Column decode circuitry is introduced as an intermediary component between the sense amplifiers and the external processing resources. This intermediary performs the matrix configuration ordering of data bits, enabling improved throughput while isolating the complexity within a dedicated circuit block rather than distributing it throughout the entire system
3Device complexity
If processing resources receive data requiring reordering, then memory device simplicity is maintained, but the number of processing steps increases
Solution Approach 1:
The memory device performs preliminary ordering of data bits in a matrix configuration before data leaves the memory device. The column decode circuitry receives data from sense amplifiers and orders it according to a matrix configuration corresponding to the arithmetic operations, so that processing resources receive pre-ordered data and don't need to perform reordering steps
Data Source
AI summary
Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.