Memory Controller Bit Prioritization for 5G NR Throughput
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Solution Overview
Problem
The increasing data rates in new radio access technologies, such as 5G NR, pose challenges in designing hardware to efficiently manage memory operations, particularly for HARQ mechanisms, leading to congestion and high memory demands.
Innovation Solution
A method and controller system that prioritize the storage and retrieval of most significant bits of data sets first, followed by subsequent bits, to optimize memory operations and reduce congestion by adaptive compression and reordering techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory operations are used to handle high data rates in 5G NR, then throughput requirements can be met, but memory congestion increases and hardware complexity rises
Solution Approach 1:
The patent segments data into data sets with multiple bits, where each data set is processed and stored in separate operations. This allows the system to manage high throughput by dividing large data transfers into smaller, manageable units that can be handled more efficiently by the memory controller, reducing overall hardware complexity.
Solution Approach 2:
The patent implements preliminary actions by pre-identifying multiple data sets before memory operations occur and pre-determining the order in which bits should be accessed. This allows the memory controller to prepare access patterns in advance, reducing real-time processing complexity while maintaining high throughput performance.
2Reliability
If all bits of data sets are stored and accessed sequentially, then data integrity is maintained, but memory access time and congestion increase
Solution Approach 1:
The patent applies local quality by treating different bits within data sets differently based on their importance and access patterns. Most significant bits are accessed and stored first, while less significant bits are handled subsequently. This differentiated approach maintains data integrity for critical portions while reducing access time for complete data sets.
Solution Approach 2:
The patent performs preliminary identification and ordering of data sets before actual memory access occurs. By pre-determining which bits need to be accessed first and preparing the access sequence in advance, the system reduces actual memory access time while ensuring all data is eventually retrieved intact.
3Productivity
If higher data rates are implemented for 5G NR, then throughput improves, but memory congestion effects worsen
Solution Approach 1:
The patent segments memory operations into discrete data set-level operations, where each data set is processed independently. This segmentation allows the memory controller to manage high throughput by handling smaller units, preventing the kind of congestion that would occur with monolithic data transfers.
Solution Approach 2:
The patent implements dynamic control of memory operations by adjusting the order and timing of bit access based on current system conditions. The controller can dynamically prioritize certain data sets or bits over others, adapting to varying load conditions to prevent memory congestion even at high data rates.
Data Source
AI summary
Methods and controllers for controlling memory operations wherein a plurality of data sets are stored in memory or read from memory by storing or reading the most significant bits of each data set first, and subsequently storing or reading the next most significant bits of the each data set.