Memory Bit Cell Selection Logic for Low-Power Programming
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Solution Overview
Problem
Programming of memory bit cells in non-volatile memory devices consumes significant power due to the unnecessary activation of entire rows and columns within the memory array.
Innovation Solution
Incorporation of a logic gate into each memory bit cell and the use of second word lines oriented substantially perpendicular to bit lines, allowing for individual selection and programming of memory bit cells without activating entire rows or columns, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If entire rows and columns are activated for programming memory bit cells, then all bit cells in the row and column can be accessed, but power consumption increases significantly
Solution Approach 1:
The memory array is segmented into smaller selectable units using additional word lines and bit lines. Instead of activating entire rows and columns, the invention enables selective activation of specific memory bit cells by dividing the address space and using segmented decoding, where only the necessary segment containing the target bit cell is activated.
Solution Approach 2:
The invention implements local quality by enabling selective activation of only the specific memory bit cell or small group of bit cells that need programming, rather than activating entire rows and columns. This is achieved through additional decoding logic that locally activates only the necessary transistors and memory cells, reducing capacitive loading on unnecessary lines.
2Use of energy by moving object
If additional logic gates and word lines are added to each memory bit cell for selective activation, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The additional word lines and logic gates are designed to serve multiple functions: they enable selective bit cell activation for power reduction, maintain compatibility with existing memory array structures, and support both read and write operations. The decoding logic universally handles address decoding across the entire memory array while enabling fine-grained selection.
Data Source
AI summary
Systems, devices, and methods are described herein for a programmable memory array. A programmable memory system includes an array of programmable memory bit cells. A memory bit cell of the array includes a first transistor of a first type controlled by a bit line, a second transistor of a second type responsive to a first word line and a second word line via a logic gate, and a third transistor of the second type responsive to the word line. The first word line is positioned substantially perpendicular to the bit line, and the second word line is positioned substantially parallel to the bit line. The first word line is activated via an X portion of an address. While the second word line is activated via a Y portion of the address.