Memory Bitcell Masking With Via Marking for OPC Alignment

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Solution Overview

Problem

Conventional memory circuitry, particularly in ROM devices, requires multiple masks for each metal layer during programming and reprogramming, which is inefficient and affected by Optical Proximity Correction (OPC), leading to alignment issues in via positioning.

Innovation Solution

Implement a via marking layer to decouple the optical proximity correction of metal layers from the via programming layer, allowing for a single via programming mask to be used, thereby reducing the number of masks needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple masks are used for each metal layer during programming, then via positioning can be achieved, but the number of masks increases and alignment errors due to OPC occur

Engineering Contradiction:

Improvevia positioning accuracyVSAvoidnumber of masks

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the masking process into two independent parts: a via marking layer that defines via positions (used for OPC control of metal layers) and a via programming layer that actually programs the vias. This segmentation allows the via marking layer to be used repeatedly for multiple metal layers without requiring separate masks for each metal layer, thus reducing the total number of masks while maintaining positioning accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The via marking layer acts as an intermediary between the via programming layer and the metal layers. It serves as a reference structure that controls OPC for multiple metal layers, eliminating the need for each metal layer to have its own dedicated mask for via positioning. This intermediary structure resolves the conflict between positioning accuracy and mask complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If multiple masks are used for programming and reprogramming, then complete programming can be achieved, but fabrication efficiency decreases

Engineering Contradiction:

Improveprogramming completenessVSAvoidfabrication efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The via marking layer is formed in advance before the via programming layer and metal layers. This preliminary structure serves as a reusable template for positioning vias across multiple programming and reprogramming operations. By establishing the via position reference early, the patent enables efficient subsequent programming operations without requiring new masks each time, thus improving fabrication efficiency while ensuring complete programming.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If via programming mask is combined with metal layer masks, then alignment can be maintained, but the number of programming masks increases

Engineering Contradiction:

Improvealignment accuracyVSAvoidmasking process time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent merges the via positioning function with the via marking layer, which is separately formed and then used to control OPC for all metal layers. Instead of combining via programming masks with each metal layer mask (which would multiply the number of masks), the via marking layer serves as a unified reference for all metal layers, maintaining alignment accuracy while reducing total masking process time.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12424292B2Masking techniques for memory applications

Publication Date: 2025.09.23 ARM LTD

AI summary

Various implementations described herein are related to a device including a bitcell having a bitcell layout with a first metal layer, a second metal layer and a via programming layer. The device may have a via marking layer provided in the bitcell layout for the bitcell, and the via marking layer controls optical proximity correction of the first metal layer and the second metal layer.