Semiconductor Memory Bit Line Spacers With Air Gap for Landing Pad Margin
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Solution Overview
Problem
The integration of semiconductor devices is hindered by the need for new and expensive exposure techniques, making it challenging to achieve high integration with reduced line widths, and existing methods lack sufficient process margins for landing pads, affecting reliability and efficiency.
Innovation Solution
A semiconductor memory device design that includes impurity doped regions, bit lines, storage node contacts, spacers, and an air gap region, with specific spacer heights and configurations to enhance process margins and reduce parasitic capacitance, allowing for improved etching control and high integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If new exposure techniques and expensive exposure systems are used to print fine patterns, then manufacturing precision is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent segments the bit line structure into multiple components: the bit line itself, a bit line capping pattern on top, and spacer structures on sidewalls. This segmentation allows each component to be formed and controlled independently, enabling precise pattern formation without requiring advanced exposure techniques for the entire structure at once.
Solution Approach 2:
The bit line capping pattern is formed preliminarily on the bit line before forming the spacers. This preliminary action establishes a defined template that guides subsequent spacer formation, ensuring precise positioning and dimensions of the spacers relative to the bit line without requiring complex real-time control during spacer formation.
2Reliability
If existing fabrication methods are used, then device integration is achieved, but process margin for landing pads is insufficient affecting reliability
Solution Approach 1:
The patent introduces spacers as intermediary structures between the bit line and storage node contacts. These spacers serve as protective barriers that prevent etching damage to the bit line sidewalls during landing pad formation, thereby increasing process margin and reliability without significantly complicating the fabrication process.
Solution Approach 2:
The spacers are formed beforehand to cushion and protect the bit line sidewalls from potential etching damage during subsequent landing pad etching processes. This prior protective measure ensures that even if etching conditions vary, the bit line remains intact, increasing process robustness and yield.
3Area of moving object
If line widths are reduced for high integration, then device integration density is improved, but new expensive exposure techniques are required
Solution Approach 1:
The patent extends the structure into the vertical dimension by adding the bit line capping pattern on top of the bit line and spacers on the sidewalls. This three-dimensional approach allows for high integration density without requiring proportionally smaller lateral dimensions, thereby avoiding the need for expensive advanced exposure techniques while still achieving high device density.
Data Source
AI summary
Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.