Memory Device Global Bit Line Charge Sharing

Solution Overview

Problem

As memory devices increase in size to provide greater storage capacity, the distances between read and write circuits and memory cells grow, leading to increased capacitance and current consumption, which deteriorates current performance and generates power noise.

Innovation Solution

A memory device design where global bit lines share electric charge, with primary and secondary charging mechanisms reducing current usage by allowing the same charge amount to be achieved with less secondary current, and precharging techniques are used to optimize current supply during read and write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory device size is increased to provide greater storage capacity, then storage capacity is improved, but current consumption increases and current performance deteriorates

Engineering Contradiction:

Improvestorage capacityVSAvoidcurrent consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The first global bit line is precharged with electric charge before the second global bit line is charged. This preliminary charging action allows the second global bit line to share the precharged electric charge, reducing the amount of current needed for charging and thereby reducing overall current consumption while maintaining the ability to serve expanded memory capacity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The first global bit line and the second global bit line share the primarily charged electric charge. By merging the charging resources, the system reduces redundant current consumption that would occur if each global bit line were charged independently, thus addressing the increased current consumption problem while supporting expanded storage capacity.

Inventive Principle:

Principle #5Merging (Combining)

2Quantity of substance

If memory device size is increased to provide greater storage capacity, then storage capacity is improved, but distance between read/write circuit and memory cell increases

Engineering Contradiction:

Improvestorage capacityVSAvoiddistance between read/write circuit and memory cell

Core Design Contradiction:

Quantity of substanceVSLength of stationary object

Solution Approach 1:

The bit line structure is segmented into local bit lines and global bit lines, with global bit lines serving multiple local bit lines. This segmentation allows the read/write circuit to interface with global bit lines at a central location while still accessing distant memory cells through the hierarchical structure, effectively managing the increased distances caused by expanded memory capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical structure with local and global bit lines, adding a dimensional layer to the bit line organization. This dimensional change allows efficient routing and charging strategies where global bit lines can be precharged and shared, reducing the impact of increased physical distances on current consumption and access time.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If global bit lines are charged independently, then charging is simple, but current consumption increases

Engineering Contradiction:

Improvecharging simplicityVSAvoidcurrent consumption

Core Design Contradiction:

Ease of manufactureVSUse of energy by moving object

Solution Approach 1:

The first global bit line is precharged with electric charge before the second global bit line is charged. This preliminary charging action allows the second global bit line to share the precharged electric charge, reducing the amount of current needed for charging and thereby reducing overall current consumption while maintaining the ability to serve expanded memory capacity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The first global bit line and the second global bit line share the primarily charged electric charge. By merging the charging resources, the system reduces redundant current consumption that would occur if each global bit line were charged independently, thus addressing the increased current consumption problem while supporting expanded storage capacity.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design significantly reduces operating current consumption, enhancing memory device performance and minimizing power noise while maintaining effective read and write operations.

Implementation Method 1

The first global bit line and the second global bit line may share the primarily charged electric charge

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9305608B2Memory device with reduced operating current

Publication Date: 2016.04.05 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device may including a first local bit line electrically connected with a first memory cell, a first global bit line electrically connected with the first local bit line, a second local bit line electrically connected with a second memory cell, and a second global bit line electrically connected with the second local bit line. The first global bit line is primarily charged with electric charge. The first global bit line and the second global bit line share the primarily charged electric charge. The second global bit line is secondarily charged with the electric charge.