Nonvolatile Memory Bitline Charging Circuit
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Solution Overview
Problem
Conventional electrically writable nonvolatile memories experience access delays due to the time required to determine whether a bit 'zero' has been read, as current flows until the bitline is charged after reading a bit 'one', necessitating a 70 nanosecond delay.
Innovation Solution
The implementation of a nonvolatile memory with a memory cell array connected to wordlines and bitlines, featuring a selector, transfer circuit, amplifier section, charger, and discharger to control bitline potential, allowing for rapid charging and discharging of bitlines and reference bitlines during wordline switching, thereby reducing access delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional reading operations are performed without additional charging/discharging circuits, then the memory structure remains simple, but access delay increases to 70 nanoseconds due to bitline charging time
Solution Approach 1:
The charger circuit pre-charges the bitline to a predetermined voltage level before the reading operation begins. This preliminary charging action eliminates the need for the bitline to charge during the reading process, thereby reducing access delay. The charger is activated in advance to ensure the bitline is ready for immediate reading.
Solution Approach 2:
The charger and discharger circuits act as intermediary components between the bitline and the reading amplifier. These intermediary circuits control the voltage levels of the bitline and reference bitline, facilitating faster and more controlled reading operations by mediating the charge/discharge processes that would otherwise occur passively.
2Speed
If the bitline is charged during reading operations to determine bit 'zero' status, then reading accuracy is maintained, but reading speed decreases due to the time required for charging
Solution Approach 1:
The charger circuit performs the charging action before the reading operation starts, so that when reading begins, the bitline is already at the appropriate voltage level. This separates the charging function from the reading function, allowing both to occur simultaneously without interfering with each other, thus maintaining both speed and accuracy.
Solution Approach 2:
The charger circuit ensures continuous availability of properly charged bitlines by pre-charging them before reading operations. This continuous preparation eliminates interruptions in the reading process that would otherwise occur while waiting for the bitline to charge, maintaining continuous useful action throughout the reading operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces access delays by quickly charging and discharging bitlines and reference bitlines, enhancing the speed of data reading operations.
Implementation Method 1
a charger for charging the bitline selected by the selector
Implementation Method 2
a discharger for discharging the reference bitline
Data Source
AI summary
A nonvolatile memory includes a memory cell array in which a plurality of memory cells are connected to a plurality of wordlines and a plurality of bitlines respectively intersecting at a right angle with the plurality of wordlines; a selector for selecting one of the bitlines which is connected to first one of the memory cells in which actual data is stored; and a transfer circuit for connecting with a reference bitline which is connected to second one of the memory cells in which a reference level is stored. The nonvolatile memory further includes an amplifier section, connected to the selector and the transfer circuit, for reading out and amplifying levels of the bitline and the reference bitline and comparing the actual data with the reference level; and a charger for charging the bitline selected by the selector.