Semiconductor Memory Device Global Bit Line Charging Segmentation
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Solution Overview
Problem
As the integration density of semiconductor memory devices increases, the time required for charging global bit lines during read operations also increases, affecting the overall speed of the memory device.
Innovation Solution
The semiconductor memory device incorporates a configuration with global bit lines connected to charging circuits and memory cell arrays, where variable resistance layers are strategically placed between interconnects, allowing for charging of global bit lines at locations other than their ends, enabling faster read operations. This configuration includes a stacked body with specific conductor arrangements and charging circuits that facilitate efficient charging and data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration density of semiconductor memory device is increased, then the memory capacity is improved, but the time required for charging global bit line is increased
Solution Approach 1:
The patent divides the global bit line charging function into multiple segments by providing multiple charging circuits at different locations along the global bit line. Instead of charging from a single end point, the global bit line is segmented into multiple charging zones, each served by a dedicated charging circuit. This segmentation reduces the effective charging distance for each segment, thereby reducing overall charging time while maintaining high memory capacity through increased integration density.
Solution Approach 2:
The patent transitions from one-dimensional charging (from end to end along the global bit line) to a multi-dimensional charging approach by distributing charging circuits at multiple locations along the global bit line. This spatial distribution across different positions creates a multi-dimensional charging network that reduces the maximum charging distance and enables parallel charging operations, thus reducing total charging time while supporting higher integration density.
2Quantity of substance
If the integration density is increased, then the memory cell density is improved, but the read operation speed is degraded
Solution Approach 1:
The patent segments the global bit line into multiple charging zones with dedicated charging circuits positioned at different locations. This segmentation enables simultaneous or near-simultaneous charging of different segments during read operations, reducing the overall time required to charge the global bit line and thereby improving read operation speed while maintaining high memory cell density.
Solution Approach 2:
The charging circuits are positioned and configured to perform preliminary charging actions on their respective segments of the global bit line before read operations commence. By having charging circuits ready at multiple locations, the system can pre-charge or quickly charge specific segments as needed, reducing wait time and improving overall read operation speed without sacrificing memory cell density.
Data Source
AI summary
A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a surface of the substrate and spaced from one another in second and third directions intersecting the first direction and each other, the stacked body having a first region and a second region, a plurality of second conductors extending in the second direction, a plurality of third conductors extending in the third, each third conductor connected to a first end, in the second direction, of a plurality of second conductors in the first region, a plurality of fourth connectors extending in the first direction, each fourth conductor connected to the plurality of second conductors in the second region, and memory cells located between adjacent surfaces of the first and second conductors in the first region.