Memory Cell Programming With Bitline Offset for Convergence Control
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Solution Overview
Problem
Existing memory devices face challenges in maintaining narrow threshold voltage distributions due to cell-to-cell interference and lateral charge migration, leading to RWB degradation and increased error rates, which affect memory device reliability.
Innovation Solution
A new program convergence scheme that adjusts the bitline voltage of memory cells using programming level information of adjacent cells, applying an analog bitline voltage offset to compensate for cell-to-cell coupling, thereby tightening the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional programming is used, then programming speed is maintained, but threshold voltage distribution widens due to cell-to-cell interference and lateral charge migration
Solution Approach 1:
The patent implements dynamic bitline voltage adjustment during programming operations. The system transitions from static voltage levels to dynamic voltage modulation, where the bitline voltage is adjusted in real-time based on the programming state and neighboring cell conditions. This dynamic approach allows the system to maintain narrow threshold voltage distributions while preserving programming speed by optimizing voltage levels throughout the programming process.
Solution Approach 2:
The patent changes the voltage parameter of the bitline during programming operations. By applying adjusted bitline voltage levels that account for cell-to-cell coupling effects, the system compensates for threshold voltage shifts caused by neighboring cell programming. This parameter change enables precise control over threshold voltage distribution without sacrificing programming throughput.
2Manufacturing precision
If bitline voltage is adjusted to compensate for cell coupling, then threshold voltage distribution narrows, but programming complexity increases
Solution Approach 1:
The patent applies local quality by adjusting bitline voltage specifically for cells affected by cell-to-cell interference rather than uniformly across all cells. The system identifies which cells require voltage compensation based on their proximity to being programmed and applies adjusted voltage levels only to those specific cells. This localized approach narrows threshold voltage distributions while minimizing the overall complexity increase.
Solution Approach 2:
The patent implements feedback mechanisms where the programming status of neighboring cells is monitored and used to adjust bitline voltage for target cells. This feedback loop allows the system to automatically compensate for cell coupling effects without requiring complex external control, as the adjustment is based on real-time information about the programming state of adjacent cells.
3Productivity
If programming operations are performed on adjacent cells, then throughput is maintained, but error rate increases due to cell-to-cell interference
Solution Approach 1:
The patent applies preliminary anti-action by pre-adjusting the bitline voltage before programming operations on adjacent cells. By anticipating the cell-to-cell interference that will occur during concurrent programming operations, the system proactively compensates for the expected threshold voltage shifts. This preliminary adjustment maintains programming throughput while preventing error rate increases by counteracting interference before it affects the programmed cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves memory device reliability by narrowing the threshold voltage distribution, reducing error rates, and enhancing programming speed without reducing throughput.
Implementation Method 1
causing an adjusted analog bitline voltage to be applied to the memory cell during a second programming pulse
Data Source
AI summary
A memory device including a memory array including a memory cell connected to a target wordline; and a first wordline adjacent to the target wordline, wherein the first wordline is to be programmed immediately subsequent to the target wordline; and control logic, operatively coupled with the memory array, to perform operations including causing a first programming pulse to be applied to the target wordline associated with the memory cell; causing a program verify operation to be performed on the memory cell to verify programming of the memory cell to a target programming level; determining that a measured threshold voltage of the memory cell satisfies a threshold criterion; identifying a fixed bitline bias level associated with the memory cell; identifying, based on programming level information of the first wordline, a bitline voltage offset associated with the memory cell; and causing, during applying a second programming pulse, an adjusted analog bitline voltage to be applied to the memory cell, wherein the adjusted analog bitline voltage is based on the fixed bitline bias level adjusted by the bitline voltage offset.