3D Memory Bit Line Structure With Dielectric Isolation

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Solution Overview

Problem

Conventional three-dimensional semiconductor storage apparatuses face challenges in improving performance due to coupling effects and parasitic capacitance between adjacent bit lines, which are exacerbated by the use of materials with low resistance to maintain small distances between bit lines.

Innovation Solution

A forming method for a semiconductor structure involving lateral etching through trenches to form cavities and bit line layers, using a specific arrangement of trenches and sacrificial layers to alleviate coupling effects and reduce parasitic capacitance, including the use of low dielectric constant materials and conductive materials like tungsten.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the distance between adjacent bit lines is reduced to improve integration density, then the integration density is improved, but the coupling effect and parasitic capacitance between bit lines increases

Engineering Contradiction:

Improveintegration densityVSAvoidcoupling effect and parasitic capacitance

Core Design Contradiction:

Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a dielectric layer as an intermediary substance between adjacent bit lines. This dielectric layer acts as a mediator that reduces the direct electromagnetic coupling between bit lines while allowing them to remain in close proximity, thereby maintaining high integration density while reducing parasitic capacitance and coupling effects.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the dielectric parameter (permittivity) of the material between bit lines by using a dielectric layer with specific electrical properties. This parameter change reduces the capacitance between adjacent bit lines without requiring increased spacing, thus resolving the contradiction between integration density and parasitic capacitance.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If materials with low resistance are used to maintain small distances between bit lines, then the electrical conductivity is improved, but the coupling effect and parasitic capacitance increases

Engineering Contradiction:

Improveelectrical conductivityVSAvoidcoupling effect and parasitic capacitance

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The dielectric layer serves as an intermediary that decouples the electrical interaction between adjacent bit lines. This allows the bit lines to be positioned close together for low resistance and high conductivity while the dielectric prevents direct capacitive coupling, thus improving electrical reliability without increasing parasitic effects.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of manufacture

If conventional three-dimensional semiconductor storage apparatus structures are used, then the manufacturing process is simplified, but the performance and parasitic capacitance reduction is limited

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidperformance and parasitic capacitance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The dielectric layer is formed between the bit lines during the manufacturing process, before the bit lines are fully assembled and operational. This preliminary action of introducing the dielectric during fabrication ensures that the low-parasitic capacitance structure is built-in from the start, achieving both manufacturing feasibility and performance improvement.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces parasitic capacitance and coupling effects between bit lines, enhancing the performance of semiconductor structures by improving reliability and reducing resistance.

Implementation Method 1

using low dielectric constant materials to alleviate coupling effects and reduce parasitic capacitance

Methodology Applied

Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20250324574A1Semiconductor structure and forming method therefor, and memory

Publication Date: 2025.10.16 RUILI INTEGRATED CIRCUIT CO LTD

AI summary

Embodiments of the present disclosure disclose a semiconductor structure and a forming method therefor, and a memory. The forming method includes the steps as follows. An initial stacked structure is provided, where the initial stacked structure includes first sacrificial layers and second sacrificial layers that are alternately stacked; multiple first trenches running through the initial stacked structure are formed; lateral etching is performed through the first trenches to remove first portions of each of the first sacrificial layers to form multiple first filling regions; a dielectric layer is formed in each of the first filling regions; the second sacrificial layers are removed to form multiple second filling regions, and a bit line layer is formed in each of the second filling regions; and a retained second portion of each of the first sacrificial layers is removed to form multiple cavities.