Non-Volatile Memory Bit Line Redundancy for Double-Error Recovery
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Solution Overview
Problem
Non-volatile memory bit lines can become defective due to short-circuits, leading to data loss and compromising error correction mechanisms, as conventional error correction codes can only correct single errors effectively.
Innovation Solution
An automatic bit line redundancy mechanism is implemented, where a redundant bit line is assigned to a defective bit line, and values are copied or inverted to correct errors, enabling double error correction without compromising the single error correction capacity of the SEC-DED system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a redundant bit line is assigned and values are copied to correct errors, then double error correction capability is achieved, but the device complexity increases
Solution Approach 1:
The patent implements a redundant bit line mechanism where values from defective bit lines are copied to redundant bit lines. The controller detects errors in words read from memory cells connected to defective bit lines, identifies the position of erroneous bits, and copies corrected values to corresponding positions in the redundant bit line, thereby achieving double error correction capability
Solution Approach 2:
The patent performs preliminary error detection and correction by reading words from memory cells connected to defective bit lines before final data retrieval. The controller proactively identifies erroneous bits, determines their positions, and prepares corrected values in the redundant bit line in advance, so that when data is retrieved, the correction is already in place
2Reliability
If bit line defects are detected and managed, then data integrity is improved, but the operation time increases due to additional detection and copying steps
Solution Approach 1:
The patent maintains continuous useful action by integrating error detection and correction into the normal read operation flow. When a word is read from memory cells connected to a defective bit line, the controller continuously monitors for errors, identifies them, and copies corrected values to the redundant bit line without interrupting the overall data retrieval process, ensuring uninterrupted data access
Solution Approach 2:
The patent efficiently copies corrected values from defective bit lines to redundant bit lines only when errors are detected. The controller reads words, detects erroneous bits, and performs selective copying of corrected values to the redundant bit line, minimizing the time overhead by only executing the copying operation when necessary rather than continuously
Data Source
AI summary
A method can be used for managing the operation of a non-volatile memory equipped with a system for correction of a single error and for detection of a double error. In the case of the detection of a defective bit line of the memory plane, a redundant bit line is assigned and the values of the bits of the memory cells of the defective line are copied into the memory cells of the redundant line and are inverted in the case of the detection of double errors by the system, or corrected by the system in the presence of single errors.