Memory Bit-Line Equalization for Low-Power Intermediate Pre-Charge

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Solution Overview

Problem

Conventional memory systems face excessive power consumption during double pumping operations due to the need for pre-charging bit lines to the supply voltage level, making it impracticable for high-density semiconductor technology.

Innovation Solution

Implementing circuits that skip full pre-charging of bit lines between operations and instead equalize the voltage between bit line pairs during intermediate pre-charge, using transistors to maintain a stable margin for memory cell operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If full pre-charging of bit lines to supply voltage is performed during double pumping operations, then operational stability is maintained, but power consumption becomes excessive

Engineering Contradiction:

Improveoperational stabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by performing only intermediate pre-charge operations instead of full pre-charging to supply voltage. The bit lines are charged to an intermediate voltage level that is sufficient for stable memory cell operation but lower than the full supply voltage, thereby reducing power consumption while maintaining operational reliability

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the voltage parameter from full supply voltage to an intermediate voltage level. By adjusting the pre-charge voltage to an optimized intermediate level, the system achieves both power reduction and operational stability, resolving the contradiction between these two requirements

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If intermediate pre-charge operations are implemented to reduce power consumption, then power efficiency improves, but voltage stability margin must be carefully controlled

Engineering Contradiction:

Improvepower consumptionVSAvoidvoltage control complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent introduces an intermediate voltage level as a mediator between ground and full supply voltage. This intermediate level serves as a compromise that reduces power consumption while maintaining sufficient voltage margin for stable operation, avoiding the need for complex dynamic voltage adjustment mechanisms

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250364021A1Low power intermediate pre-charge operations in memory

Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Memory devices, circuits, and a method of operating the same are disclosed. In one aspect, a memory device includes a memory cell coupled between a first bit line and a second bit line. The memory cell includes a write circuit configured to write data to the memory cell via the first bit line and the second bit line during a write operation. The memory cell includes a voltage equalizing device configured to equalize the voltage of the first bit line and the second bit line following the write operation and prior to a second memory operation for the memory cell.