Memory Bit Line Structure With Gap Isolation for Lower Parasitic Capacitance
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Solution Overview
Problem
As memory process nodes continue to shrink, the increasing parasitic capacitance between bit lines leads to slow operating speeds and high power consumption, while etching methods introduce impurities and structural issues like tilting and collapse, affecting yield and lifespan.
Innovation Solution
A manufacturing method that forms a gap between the bit line conductive portion and the dielectric layer, fills the bit line conductive portion through a hole rather than etching, and uses sacrificial layers for support, reducing parasitic capacitance, impurity incorporation, and structural instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory process node is reduced to improve integration density, then manufacturing precision is improved, but parasitic capacitance between bit lines increases causing slower operating speed and higher power consumption
Solution Approach 1:
The bit line structure is segmented into discrete bit line contact layers separated by gaps, rather than continuous structures. This segmentation reduces parasitic capacitance between adjacent bit lines while maintaining integration density through precise spatial arrangement of the segmented elements.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between adjacent bit line conductive portions. This dielectric layer acts as an electrical insulator that reduces parasitic capacitance coupling between bit lines, thereby improving operating speed while allowing continued scaling.
2Manufacturing precision
If etching method is used to form bit line structure, then manufacturing precision is improved, but impurities are introduced and structural stability deteriorates
Solution Approach 1:
The mechanical etching process is replaced with a deposition-based formation method. Bit line conductive portions are formed by depositing conductive material in defined regions rather than removing material through etching, which eliminates impurity introduction and avoids structural tilting or collapse associated with etching.
Solution Approach 2:
Dummy bit line structures are formed preliminarily as templates before the actual bit line conductive portions are created. These dummy structures guide the formation process and ensure precise positioning, allowing the bit lines to be formed without relying on etching that could compromise structural stability.
3Area of stationary object
If bit line contact layers are placed closer together to improve integration density, then area is reduced, but parasitic capacitance increases causing higher power consumption
Solution Approach 1:
The dielectric layer is applied locally between adjacent bit line contact layers rather than uniformly throughout the structure. This localized dielectric insertion reduces parasitic capacitance precisely where needed between closely spaced bit lines, enabling high integration density without excessive power consumption.
Solution Approach 2:
The solution moves from a two-dimensional planar arrangement to a three-dimensional structure by adding vertical spacing through the dielectric layer. This dimensional approach allows bit lines to be placed closer in the planar view while maintaining electrical isolation through the vertical dielectric barrier, reducing parasitic capacitance.
Data Source
AI summary
A manufacturing method of a memory includes: providing a substrate and a bit line contact layer; forming a dummy bit line structure on top of the bit line contact layer; forming a spacer layer on the sidewall of both the dummy bit line structure and the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer filling the area between adjacent dummy bit line structures, wherein the sacrificial layer covers the sidewall of the dielectric layer; after the sacrificial layer is formed, removing the dummy bit line structure; forming a bit line conductive portion which fills the hole and covers the bit line contact layer; and, after the bit line conductive portion is formed, removing the spacer layer.