Semiconductor Memory Device Bit Line Precharge Overlap
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Solution Overview
Problem
Semiconductor memory devices, particularly three-dimensional flash memory devices, face challenges in reducing the time required for bit line precharge operations during program and read operations, which affects their operating speed.
Innovation Solution
The semiconductor memory device incorporates control logic that allows the word line overdrive period to partially overlap with the bit line overdrive period during bit line precharge operations, enabling efficient application of overdrive voltages to both word lines and bit lines, thereby reducing the time needed for precharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the bit line precharge operation is performed sequentially without overlapping with word line overdrive period, then the operation is simple to control, but the precharge time is extended
Solution Approach 1:
The patent merges the bit line precharge operation with the word line overdrive operation by overlapping their time periods. The control logic is designed to simultaneously activate the bit line precharge transistors and apply overdrive voltage to the word line, combining two operations that were previously performed sequentially. This overlapping execution reduces the total precharge time while the control logic coordinates both operations through shared control signals.
Solution Approach 2:
The patent applies preliminary action by starting the bit line precharge operation before the word line overdrive period ends. The control logic initiates the precharge transistors during the word line overdrive period, allowing the bit lines to begin charging in advance. This preliminary action enables the precharge to complete faster by utilizing the time overlap with the word line overdrive period.
2Reliability
If the word line overdrive period is extended to ensure complete precharge, then the precharge operation is reliable, but the operating speed is reduced
Solution Approach 1:
The patent maintains continuity of useful action by keeping the bit line precharge transistors active throughout the overlapping period with the word line overdrive. Instead of completing the precharge early and then waiting for the overdrive period to end, the system continues the precharge action continuously during the overlap, ensuring reliable completion while utilizing the available time efficiently. This continuous action guarantees proper precharge without unnecessarily extending the total operation time.
3Productivity
If overdrive voltage is applied to both word line and bit line simultaneously, then the precharge operation is accelerated, but the power consumption increases
Solution Approach 1:
The patent applies partial overdrive action by using overdrive voltage on the word line during the overlapping period while the bit lines are being precharged. The overdrive voltage is applied selectively to the word line rather than simultaneously to all bit lines, providing accelerated precharge where needed while limiting the overall power consumption. This partial application of excessive voltage achieves speed improvement without proportionally increasing power usage.
Data Source
AI summary
A semiconductor memory device, and a method of operation, include: a memory block coupled with a plurality of word lines and a plurality of bit lines; a peripheral circuit configured to perform a program operation and a read operation on the memory block; and control logic configured to control the peripheral circuit such that a word line overdrive period overlaps with a bit line overdrive period in a bit line precharge operation during at least one of the program operation and the read operation.