Non-Volatile Memory Bit Line Timing for Stable Programming
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Solution Overview
Problem
The program operation in nonvolatile memory devices is unstable due to potential level disturbances on bit lines caused by coupling effects between adjacent bit lines during the bit line setup and program pulse application intervals.
Innovation Solution
A memory device and method that stabilizes bit line potentials by connecting bit lines to specific voltage nodes during distinct time intervals, including connecting first and second bit lines to a permission voltage and a third bit line to a prohibition voltage, and maintaining these connections during program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit lines are left floating during program operation, then the device structure remains simple, but potential level disturbances occur due to coupling effects between adjacent bit lines
Solution Approach 1:
The patent applies preliminary action by setting the potential levels of bit lines before the program pulse is applied. Specifically, during a setup interval before the program operation, the bit line control circuit connects selected bit lines to permission voltage nodes and unselected bit lines to prohibition voltage nodes, ensuring that potential levels are established in advance to prevent coupling-induced disturbances during the actual program operation.
Solution Approach 2:
The patent introduces an intermediary element - the bit line control circuit - that mediates between the simple floating bit line structure and the need for stable potential levels. This control circuit selectively connects bit lines to different voltage nodes (permission or prohibition) based on whether they are selected or unselected, thereby preventing harmful coupling effects without requiring complex restructuring of the memory cell array.
2Reliability
If potential levels of bit lines are stabilized during program operation, then program operation becomes reliable, but the control mechanism becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the bit line control into distinct segments: selected bit lines are connected to permission voltage nodes while unselected bit lines are connected to prohibition voltage nodes. This segmentation allows independent control of different bit line groups, enabling stable potential levels during program operation through a manageable control structure rather than a monolithic complex system.
Solution Approach 2:
The patent implements periodic action through time-divided control: during a setup interval before the program pulse, bit lines are configured to appropriate voltage nodes; during the program pulse application interval, the configuration is maintained; and after the program operation, the bit lines can be reconfigured. This periodic switching approach enables reliable program operation while keeping the control mechanism temporally organized and manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents bit line floating and ensures stable potential levels, enabling reliable data storage in nonvolatile memory devices.
Implementation Method 1
a phenomenon in which the targeted potential levels of the bit lines are disturbed without maintaining the potential levels may occur due to a coupling effect between adjacent bit lines
Data Source
AI summary
A memory device comprising: a memory cell array, and a controller configured to connect, in a first interval equal to or longer than a bit line setup interval, each of first and second bit lines, which are connected to cells respectively having first and second program states, to a node of a first permission voltage, connect, in the first interval, a third bit line, which is connected to a cell having a program prohibition state, to a node of a prohibition voltage, maintain, in a second interval that is equal to or shorter than a program pulse application interval, the respective connections of the first bit line and the third bit line, and disconnect, in the second interval, the second bit line from the node of the first permission voltage to apply the second bit line with a second permission voltage.