Dual-Sided Memory Bit Line Layout for Lower RC Loading
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices affects the operating voltages and overall performance, leading to inefficiencies.
Innovation Solution
The configuration of bit lines on both the front-side and back-side of a substrate, with one set on a metal layer above the front-side and another on a metal layer below the back-side, reduces resistance capacitance (RC) loading, thereby increasing speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If ICs become smaller and more complex, then device functionality and integration are improved, but resistance of conductive lines increases affecting operating voltages and performance
Solution Approach 1:
The patent utilizes both front-side and back-side of the substrate to route bit lines, effectively adding a dimensional aspect to the interconnect architecture. By placing bit lines on metal layers at both front and back sides of the substrate, the design distributes conductive paths across multiple spatial dimensions, reducing resistance and voltage drops while maintaining high integration density.
2Speed
If bit lines are configured on both front-side and back-side of substrate, then RC loading is reduced and speed is increased, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent utilizes both front-side and back-side of the substrate to route bit lines, effectively adding a dimensional aspect to the interconnect architecture. By placing bit lines on metal layers at both front and back sides of the substrate, the design distributes conductive paths across multiple spatial dimensions, reducing resistance and voltage drops while maintaining high integration density.
Solution Approach 2:
The bit line configuration is segmented into multiple sets: first set on front-side metal layer, second set on back-side metal layer. This segmentation allows each set to serve specific memory cell banks, reducing the RC loading for each segment while maintaining overall system performance.
3Use of energy by moving object
If bit lines are configured on both front-side and back-side of substrate, then power consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes both front-side and back-side of the substrate to route bit lines, effectively adding a dimensional aspect to the interconnect architecture. By placing bit lines on metal layers at both front and back sides of the substrate, the design distributes conductive paths across multiple spatial dimensions, reducing resistance and voltage drops while maintaining high integration density.
Solution Approach 2:
The manufacturing process merges front-side and back-side processing sequences, with the back-side metal layer formation building upon previously formed front-side structures. This combined approach achieves dual-sided bit line configuration while streamlining the overall manufacturing workflow.
Data Source
AI summary
A memory cell array includes a first bank of memory cells, a second bank of memory cells below the first bank of memory cells, a first and a second set of bit lines, and a first set of word lines. The first set of bit lines is coupled to the first bank of memory cells, and is on at least a first metal layer above a front-side of a substrate. The second set of bit lines extends in the first direction, is coupled to the second bank of memory cells, and is on at least a second metal layer below a back-side of the substrate opposite from the front-side of the substrate. The second set of bit lines do not extend to the first bank of memory cells. The first set of word lines is on the first metal layer, and being coupled to the first bank of memory cells.