3D Memory Bit Line Segmentation for Lower Loading Capacitance
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Solution Overview
Problem
As memory cells are integrated at a high density in memory devices, the increased number of memory cells connected to a single signal line leads to higher loading capacitance, making it difficult for bit line sense amplifiers to accurately sense voltage levels within the set sensing margin.
Innovation Solution
The memory device employs a structure where cell transistors on different levels are used as select and precharge transistors, reducing the need for additional layers and simplifying the semiconductor process, while using multiplexer circuits to connect local bit lines to a global bit line, thereby reducing loading capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are integrated at high density with more cells connected to a single signal line, then integration is improved, but loading capacitance on the signal line increases
Solution Approach 1:
The patent divides the bit line into multiple segments by introducing local bit line sense amplifiers that can independently sense voltage levels of different local bit line groups. This segmentation reduces the effective loading capacitance that any single sense amplifier must handle, as each amplifier only needs to sense a portion of the total capacitance rather than the entire high-density array.
Solution Approach 2:
The patent introduces intermediate sensing structures (local bit line sense amplifiers and associated transistors) that act as mediators between the high-density memory cells and the global bit line. These intermediaries break down the large capacitance into manageable portions, allowing accurate sensing despite the high integration density.
2Measurement precision
If additional layers are added to reduce loading capacitance, then sensing capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent designs transistors with dual functionality: they serve as both select transistors for accessing memory cells and as sensing transistors for detecting voltage levels. This multi-functionality eliminates the need for separate sensing transistor layers, reducing manufacturing complexity while maintaining accurate sensing capability. The same transistor structure performs multiple roles in the memory operation.
Solution Approach 2:
The patent merges the select transistor and sensing transistor functions into a single transistor structure. By combining these functions, the patent avoids adding extra layers or structures that would increase manufacturing complexity, while still achieving the necessary sensing precision through the integrated design.
Data Source
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AI summary
A memory device includes: local bit line structures arranged in first and second directions parallel to a surface of a substrate and intersecting each other, and extending across a plurality of vertical levels; first and second channel structures extending in the first direction on each of the plurality of levels and respectively contacting sidewalls of each of the local bit line structures and having first and second impurity regions; gate structures extending in the second direction on each of the plurality of levels, and respectively contacting the channel structures arranged in the second direction; cell capacitors in contact with the second impurity regions; first interconnection patterns respectively electrically connected to the second impurity regions on one or more first levels of the plurality of levels; and second interconnection patterns respectively electrically connected to the second impurity regions on the one or more first levels.