3D Memory Bit Line Selector Layout for Lower Routing Load
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Solution Overview
Problem
The complexity of routing channels in CMOS wafers due to the presence of global bit lines and multiplexers in semiconductor devices leads to a high load on the global bit lines, complicating the circuit design.
Innovation Solution
The semiconductor device is structured with memory array and peripheral structures on different wafers, utilizing through silicon via (TSV) technology and hybrid bonding to connect local and global bit lines through selectors, allowing flexible positioning of global and local bit line selectors, reducing routing complexity and load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If global bit lines and multiplexers are both placed in the CMOS wafer, then the circuit functionality is achieved, but the routing channels become complicated and the global bit line load increases
Solution Approach 1:
The patent divides the bit line selection functionality into two separate segments: local bit line selectors are placed on the array wafer to handle local bit line connections, while global bit line selectors are placed on the CMOS wafer to handle global bit line connections. This segmentation separates the routing complexity from the global bit lines, simplifying their paths and reducing their load while maintaining complete circuit functionality.
2Ease of operation
If all selectors are placed on the CMOS wafer, then the control logic is simplified, but the routing channels in the CMOS wafer become complicated
Solution Approach 1:
The patent segments the selector placement across two different wafers: local bit line selectors remain on the array wafer close to the memory strings, while global bit line selectors are moved to the CMOS wafer. This spatial segmentation allows control logic to be distributed appropriately, simplifying routing channels in the CMOS wafer while maintaining ease of operation through coordinated control of both selector groups.
3Device complexity
If local bit line selectors are moved to the peripheral structure, then the routing channels are simplified, but additional through holes and inter-wafer connections are required
Solution Approach 1:
The patent transitions from a planar two-dimensional routing approach to a three-dimensional approach by utilizing vertical through holes (TSVs) that pass through the array wafer. Local bit line selectors are positioned in the peripheral structure and connect to local bit lines through vertically extending first through holes, while second through holes provide inter-wafer connections to the CMOS wafer. This dimensional change simplifies routing channels by using vertical interconnects instead of complex lateral routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure simplifies the routing channels, reduces the load on global bit lines, and enhances the response speed of the memory by minimizing signal transmission distances.
Implementation Method 1
utilizing through silicon via (TSV) technology and hybrid bonding to connect local and global bit lines through selectors
Implementation Method 2
utilizing through silicon via (TSV) technology and hybrid bonding to connect local and global bit lines through selectors
Data Source
AI summary
A semiconductor device includes a memory array structure and a peripheral structure. The memory array structure includes a plurality of memory strings, a plurality of local bit lines, and a plurality of global bit lines. The peripheral structure includes a plurality of local bit line selectors and one or more global bit line selectors. Each of the local bit lines is connected with at least one of the memory strings. Each of the local bit line selectors has an output terminal connected with ones of the local bit lines respectively through first through holes, and an input terminal connected with one of the global bit lines through a second through hole. Each of the global bit line selectors has an output terminal connected with ones of the global bit lines respectively through third through holes.