Memory Bitline Shielding Structure for Interference Reduction
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Solution Overview
Problem
Semiconductor memory devices face challenges in miniaturization and lightweight design while maintaining high operation speed and reducing electrical interference between components.
Innovation Solution
The implementation of a shielding structure between memory cell arrays and global bitlines, which includes a shielding conductive plate or stripes to reduce electrical interference, and a switch circuit to stabilize capacitor electrode voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If global bitlines are positioned close to memory cell arrays to reduce device area, then area is reduced, but electrical interference between global bitlines and memory cell arrays increases
Solution Approach 1:
A shielding structure is introduced as an intermediary component between the global bitlines and the memory cell arrays. This shielding structure includes a shielding conductive plate positioned between the global bitlines and the memory cell arrays, which acts as a mediator to block or reduce electrical interference (such as capacitive coupling) between these two components, thereby allowing them to be positioned closer together without suffering from excessive interference.
2Reliability
If shielding structure is added to reduce electrical interference, then electrical performance is improved, but device complexity increases
Solution Approach 1:
The shielding conductive plate is merged with existing device structures. Specifically, the shielding conductive plate is positioned between the global bitlines and the memory cell arrays and can be integrated with interlayer insulating films or other structural elements already present in the device, thereby providing shielding functionality without adding significant structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances electrical performance by minimizing coupling capacitance and voltage fluctuations, improving the overall performance and reliability of semiconductor memory devices.
Implementation Method 1
The shielding structure is between the memory cell array and the plurality of global bitlines, and is configured to at least partially shield electrical interference between the memory cell array and the plurality of global bitlines
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a plurality of global bitlines, a plurality of local bitlines, and a shielding structure. The memory cell array includes a plurality of memory cells on a semiconductor substrate. The plurality of global bitlines are above the memory cell array in a first direction perpendicular to a top surface of the semiconductor substrate, arranged in a second direction parallel to a top surface of the semiconductor substrate, and extend in a third direction parallel to a top surface of the semiconductor substrate. The plurality of local bitlines extend in the first direction and connect the plurality of memory cells and the plurality of global bitlines. The shielding structure is between the memory cell array and the plurality of global bitlines and is configured to at least partly shield electrical interference between the memory cell array and the plurality of global bitlines.